From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 017F93128C9 for ; Tue, 3 Feb 2026 10:46:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.52 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770115603; cv=none; b=FdjEypXDwbbj0x6cPcmkAiuLB6kqL1sR9qY2B11ZHZd8C1SpZxPNBYbMivsJ+ae+fQ7BmdBEVlxb9l1DMC9bblF9aXEJGxF9S1P/Ec2DMSen5tFyt086UqEVta7KU7W6koUsOZEckGxlo4cWMSm20dNmERNJB3CThifcYkKu5qo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770115603; c=relaxed/simple; bh=dU5PMbFjeSaZiIXv05iCDeaergWDFpV7s5wXJkHJ8ik=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=ex+bzriac2QcTrRqRmwYkAsnYFLngVmbmx3QTVFzp0lfdW0Ee60vdmpBHXqQazOdRBXhNm3culdhBj8gd66LoL54nYN12L1bwNSaw/PX0HdOZfo9F1yvOGR+QJD35N8t8xXi3y+1iZ4zAtVSCkEkiZLzgG0h1DGta6XF0Nh4miA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=BcSsk+5w; arc=none smtp.client-ip=209.85.128.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="BcSsk+5w" Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-4807068eacbso45408505e9.2 for ; Tue, 03 Feb 2026 02:46:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1770115599; x=1770720399; darn=vger.kernel.org; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=R6pk37gWj4Ao60hHiNwtAWN3UnalWQ7UEtWm6JRc280=; b=BcSsk+5wuShsbHSJg8jLO+u9Y0bXnGO3u/lTU4TXhyqU/CSk7O7oI2sBA/XMT1tsgK LnQRqJn01jpMlduzn109A7BuPi1seb5b/uY3KTPtIWKRcrob0vrb9jcjOzWo8MAYzwq4 9xNqoG97gdVgVg9ruXgGp+0OU3pUVWISHYxYxNvbYR++zou9LZHLDrZPfZX1U/lYe5J0 RBCC2GRwhEM/YZn6iyk2Eq7R7ghIz73VBOVkY9PnDZbBy+pLFmS7t7CE+LglmdMmrBY1 +jF3kuvHKcwamCJo43w5oEzuxL6QVCyJpmq9HuKIsHCtR6hPW9RZQWOwt0ewnb5TVSCd PCMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770115599; x=1770720399; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :x-gm-gg:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=R6pk37gWj4Ao60hHiNwtAWN3UnalWQ7UEtWm6JRc280=; b=HHOsU0Wy6JzoNGjwmSq4gUetWd1VsSORtV9TeXz3HjIOAYMAOnIB4dSPkm+rMQfuq7 R20z7WZkA7ssAeyjP+il1Y2gbGjfcPzELdJCCgniSbkTQDxOZoac89Qd6IFuudqxkdv7 yx3c+ubnH96+l6Dn2g3a3NIfEX3RIf76afYDOw5oCh3j7ItWVxL+iJAUVmG8Nt7yRNm5 x4166diVSIUQYfg0za9KI3DbFNPX3r9Wyf4r+MGTnDaS/Jf3wh1ZlaQP9iZAE/z+12Wj m/EhVOXmoTSiwx+djR8m8Zx9Ivn5ZqxRgG6KlRkR5w0xn3xBE385U8W+AKTO3qGZWPIw V92w== X-Forwarded-Encrypted: i=1; AJvYcCXapEi/zV9prU73iJ8+gHs6mYabT7ZVkdA02/zaFM4A3Ox1WdZwru/Co24ePlXnpifB4uaMxe4CNyMdxGg=@vger.kernel.org X-Gm-Message-State: AOJu0YxMh5IIPUui6TljouoUTAxYrzOj5Y+82boDA1KfKeW/8dAYU5b0 hk9Snq0HSczcjm+m/mMoCa6jSS+KwqD87FaqMObDUmzSzySUo1YXrdVVm0nurqLolDA= X-Gm-Gg: AZuq6aIvLrEOTdgKOjla4umIteBWCVYfdl+qktc+aUDhiuZbiKs3IZafR1sXLhR4iIQ eAm5Vy34Lx8OLT+6PMHxnOuDKWjxqzzHFVNzBNdLrqcR3fi2JfFrxOS4tVcdW90FH+DNjRgRmDO rHPVXjZ0cHY94KKpgPzgPDYKAhZS92AnllLFBKaLnKt6D/g9IirMBWhZHbvBpf214v5UDeFriTd WQMmtMNhmywo1ZCoxVKrfnnbt/+K0JCHlPRg3IyoefvJ5fo172UKeBVeGnLtRorEPARIqUfogxh WH3u28ToRu3pxUtqWWg9LR9U51kkX7+01WLn8XXIA50rElZd+AWa+4SKt0AcP6RCPu9bDrf6kPr bC5BMwKg+V8yYkvq5WlXfXP2fshcyoO5FZ2ceHkyYKcY2b6HjnTev4CRf69X10nvcTfWovZWCTU /W1XkLLHGku6i/DbG38Xoblecfnws= X-Received: by 2002:a05:600c:6610:b0:47e:e076:c7a5 with SMTP id 5b1f17b1804b1-482db45211fmr187500675e9.11.1770115599291; Tue, 03 Feb 2026 02:46:39 -0800 (PST) Received: from [192.168.1.3] ([185.48.77.170]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-483051286e0sm57339175e9.5.2026.02.03.02.46.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 03 Feb 2026 02:46:38 -0800 (PST) Message-ID: Date: Tue, 3 Feb 2026 10:46:37 +0000 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] perf: arm_spe: Add barrier before enabling profiling buffer To: Will Deacon Cc: Mark Rutland , Catalin Marinas , Alexandru Elisei , Anshuman Khandual , Rob Herring , Suzuki Poulose , Robin Murphy , Leo Yan , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260123-james-spe-relaxation-v1-1-4ccb88fa7bc5@linaro.org> Content-Language: en-US From: James Clark In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 02/02/2026 7:03 pm, Will Deacon wrote: > On Fri, Jan 23, 2026 at 04:03:53PM +0000, James Clark wrote: >> The Arm ARM known issues document [1] states that the architecture will >> be relaxed so that the profiling buffer must be correctly configured >> when ProfilingBufferEnabled() && !SPEProfilingStopped() && >> PMBLIMITR_EL1.FM != DISCARD: >> >> R24557 >> >> While the Profiling Buffer is enabled, profiling is not stopped, and >> Discard mode is not enabled, all of the following must be true: >> >> * The current write pointer must be at least one sample record below >> the write limit pointer. >> >> The same relaxation also says that writes may be completely ignored: >> >> When the Profiling Buffer is enabled, profiling is not stopped, and >> Discard mode is not enabled, the PE might ignore a direct write to any >> of the following Profiling Buffer registers, other than a direct write >> to PMBLIMITR_EL1 that clears PMBLIMITR_EL1.E from 1 to 0: >> >> * The current write pointer, PMBPTR_EL1. >> * The Limit pointer, PMBLIMITR_EL1. >> * PMBSR_EL1. > > Thinking about this some more, does that mean that the direct write to > PMBPTR_EL1 performs an indirect read of PMBLIMITR_EL1 so that it can > determine the write-ignore semantics? If so, doesn't that mean that > we'll get order against a subsequent direct write of PMBLIMITR_EL1 > without an ISB thanks to table "D24-1 Synchronization requirements" > which says that an indirect read followed by a direct write doesn't > require synchronisation? > > There's also a sentence above the table stating: > > "Direct writes to System registers are not allowed to affect any > instructions appearing in program order before the direct write." > > so after all that, I'm not really sure why the ISB is required. > > Will We were under the impression that this was required for the SPU as it is treated as a separate entity than the PE. In "D17.9 Synchronization and Statistical Profiling" there is: INDWCG A Context Synchronization event guarantees that a direct write to a System register made by the PE in program order before the Context synchronization event are observable by indirect reads and indirect writes of the same System register made by a profiling operation relating to a sampled operation in program order after the Context synchronization event. That specifically mentions an indirect read following a direct write, which seems to contradict D24-1. Although I thought this is a special case for SPE.