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Mon, 20 Apr 2026 23:10:08 -0700 (PDT) Received: from hu-arakshit-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82f8ebe68ebsm13905438b3a.47.2026.04.20.23.10.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Apr 2026 23:10:08 -0700 (PDT) Date: Tue, 21 Apr 2026 11:40:00 +0530 From: Abhinaba Rakshit To: Harshal Dev Cc: Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , "James E.J. Bottomley" , "Martin K. Petersen" , Adrian Hunter , Ulf Hansson , Neeraj Soni , Kuldeep Singh , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio Subject: Re: [PATCH v8 3/5] mmc: sdhci-msm: Set ICE clk to TURBO at sdhci ICE init Message-ID: References: <20260409-enable-ice-clock-scaling-v8-0-ca1129798606@oss.qualcomm.com> <20260409-enable-ice-clock-scaling-v8-3-ca1129798606@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Proofpoint-ORIG-GUID: D_zwQ6PTe5MvVcpQFy4rojKEnAJ5BcMw X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDIxMDA1NyBTYWx0ZWRfX+BoOEJH8hGvi zJAV8mVZNJ3lPh0o8uQY2qrfStSfzQ3UHQwQAD/DZC5+cto9p5atErmYj7iIezZzO71N9u5V056 F43Wad5RBLqDeFot2E8Q1/F/vay3CzZ1we5gArTIeVQ0liiLWFO1zY4ECf0IOP9zTEHSkEAfKtF po9LCdK9w5+w4O8Yti4glK7oW+1PwKJzYIFjMtpvBEH6FlgtRrXCzVwvz/ogIb8TW92LKiatumQ aYJkk7EPzNnzr3Y3aTglHjbV4rLUfD2tNgHM82eX3l08mdKCvmIZv5s6A163RKk08vqUpV6TNz8 9dML8N4Z27iYptZKlJ8dNXGq4fA90B89i4RkmmBbSmcLNljkDEUt0n5r2TJdJfnEon3yeutRLqb FTltiLcHMsXkRG4l2wIHsNL4onBqvjRXgXonkGh9xUvIz4Mj1uUs84+Pk2lgeiiSSv6TK1mK99X 0dwD9wgDBIiC+/B2Fmw== X-Authority-Analysis: v=2.4 cv=XNMAjwhE c=1 sm=1 tr=0 ts=69e714c2 cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=kj9zAlcOel0A:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=ciROkYvXyXDSqN8Q_VUA:9 a=CjuIK1q_8ugA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-GUID: D_zwQ6PTe5MvVcpQFy4rojKEnAJ5BcMw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-21_01,2026-04-20_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 impostorscore=0 suspectscore=0 clxscore=1015 phishscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604210057 On Fri, Apr 17, 2026 at 06:59:42PM +0530, Harshal Dev wrote: > > > On 4/9/2026 5:14 PM, Abhinaba Rakshit wrote: > > MMC controller lacks a clock scaling mechanism, unlike the UFS > > controller. By default, the MMC controller is set to TURBO mode > > during probe, but the ICE clock remains at XO frequency, > > leading to read/write performance degradation on eMMC. > > > > To address this, set the ICE clock to TURBO during sdhci_msm_ice_init > > to align it with the controller clock. This ensures consistent > > performance and avoids mismatches between the controller > > and ICE clock frequencies. > > > > For platforms where ICE is represented as a separate device, > > use the OPP framework to vote for TURBO mode, maintaining > > proper voltage and power domain constraints. > > > > Reviewed-by: Konrad Dybcio > > Signed-off-by: Abhinaba Rakshit > > --- > > drivers/mmc/host/sdhci-msm.c | 24 ++++++++++++++++++++++++ > > 1 file changed, 24 insertions(+) > > > > [...] > > > > > static const struct blk_crypto_ll_ops sdhci_msm_crypto_ops; /* forward decl */ > > +static int sdhci_msm_ice_scale_clk(struct sdhci_msm_host *msm_host, unsigned long target_freq, > > + bool round_ceil); /* forward decl */ > > > > static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host, > > struct cqhci_host *cq_host) > > @@ -1964,6 +1966,11 @@ static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host, > > } > > > > mmc->caps2 |= MMC_CAP2_CRYPTO; > > + > > + err = sdhci_msm_ice_scale_clk(msm_host, INT_MAX, false); > > The 2nd parameter is an unsigned long, do you really want to pass INT_MAX here? I would go with > UINT_MAX. But still, why go with such a high value? Do we not have an upper bound for the clk > frequency that we know we can't ever exceed for any target across OPP tables? If not, then maybe > UINT_MAX is best we can do here. Ack. The scaling functions along with the OPP-helpers clamps the requested frequency to the maximum supported rate based on the clock/OPP table, so any sufficiently large value serves the purpose here. Frequencies are better represented as unsigned long values hence, will update it with something ULONG_MAX in the next patchset. Abhinaba Rakshit