From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AH8x2264lI2xFV4sWGa5IPmYODC8LmCZbKD+6H+xs2edZk7sjaIdtZ3JobiTqKdQT3ILKBHyj5ao ARC-Seal: i=1; a=rsa-sha256; t=1516557714; cv=none; d=google.com; s=arc-20160816; b=chhio089SnIwhqQkGqBpCsbygDb0Lpp2j4mJyDAQ6X1mGTbmqkUqNkhwG+8eAdPdk4 CjAMEEqU+xZCitPlMmrVL5OkTv+Hz5tMrjdlOhQcwC2lP7EE2r7VuYh7yHIelUSahQXD i81QpcWYuoE+9EZmjo7WiGFRH4Lh87bH8HBxTVbLKvZm1VQX9lQSTnJ72S3hqHEp+hhs W6ZOwmicmEMdfoj6Lhgml+Jgh0bkqrjAMWbz976XHtjc16mvSpnTO5bhJQgQEGuS9DnL Xy+gEYTb7xQA5dpqYA0BqgUMbyY5YHKPbplbgbr7OtB+11IXVzyL25ZvO78+NQ5ljiYC icow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-language:content-transfer-encoding:in-reply-to:mime-version :user-agent:date:message-id:from:references:to:subject :arc-authentication-results; bh=UP08mMz/zf/3W/55YuQuX0Db2d693U7eTVg2Jg5E0AY=; b=FmQ3xAzntlSuVr4NSXWThgsoHDoLh45KAZR2vJfNauLYGJUNIHtOotiAKpsRsbFwHd Cyzp3S3giOJuMPtG57L7BcSN+p2w/oRwhNRA8o3Z71i5cZ5KxqEau4huswvPTRncX0kk PDmeYSwJ8eS8UMeWQDg+494NSP38ioLFi652fqxrmN0a5j4b+MX7w6LsCTE+AkIbvk1e OuVM/nksocR7RoUc9LaWUKGAZ2DmkkVdiEQyw+2gMMDiZoxPcBC579F9/I+np4Dt5HVz XPCzQDsUqDAz+zECA50S4IN7uLGLuJLljnKoCMS+ElZukzXiMoUUXt5LdIXd+SvmfYG8 PpmQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of prvs=552f9dda3=andrew.cooper3@citrix.com designates 185.25.65.24 as permitted sender) smtp.mailfrom=prvs=552f9dda3=Andrew.Cooper3@citrix.com Authentication-Results: mx.google.com; spf=pass (google.com: domain of prvs=552f9dda3=andrew.cooper3@citrix.com designates 185.25.65.24 as permitted sender) smtp.mailfrom=prvs=552f9dda3=Andrew.Cooper3@citrix.com X-IronPort-AV: E=Sophos;i="5.46,392,1511827200"; d="scan'208";a="66414892" Subject: Re: [PATCH v2 2/8] x86/cpufeatures: Add AMD feature bits for Prediction Command To: Tom Lendacky , David Woodhouse , , , , , , , , , , , , References: <1516528149-9370-1-git-send-email-dwmw@amazon.co.uk> <1516528149-9370-3-git-send-email-dwmw@amazon.co.uk> From: Andrew Cooper Message-ID: Date: Sun, 21 Jan 2018 18:01:36 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.2 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Content-Language: en-GB X-ClientProxiedBy: AMSPEX02CAS01.citrite.net (10.69.22.112) To AMSPEX02CL02.citrite.net (10.69.22.126) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1590195040636439803?= X-GMAIL-MSGID: =?utf-8?q?1590226021472071392?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: On 21/01/18 17:50, Tom Lendacky wrote: > On 1/21/2018 3:49 AM, David Woodhouse wrote: >> AMD doesn't implement the Speculation Control MSR that Intel does, but >> the Prediction Control MSR does exist and is advertised by a separate >> CPUID bit. Add support for that. >> >> Signed-off-by: David Woodhouse >> --- >> arch/x86/include/asm/cpufeatures.h | 1 + >> arch/x86/kernel/cpu/scattered.c | 1 + >> 2 files changed, 2 insertions(+) >> >> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h >> index 2efb8d4..8c9e5c0 100644 >> --- a/arch/x86/include/asm/cpufeatures.h >> +++ b/arch/x86/include/asm/cpufeatures.h >> @@ -207,6 +207,7 @@ >> #define X86_FEATURE_RETPOLINE_AMD ( 7*32+13) /* AMD Retpoline mitigation for Spectre variant 2 */ >> #define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */ >> >> +#define X86_FEATURE_AMD_PRED_CMD ( 7*32+17) /* Prediction Command MSR (AMD) */ >> #define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */ >> #define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* Fill RSB on context switches */ >> >> diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c >> index df11f5d..4eb90b2 100644 >> --- a/arch/x86/kernel/cpu/scattered.c >> +++ b/arch/x86/kernel/cpu/scattered.c >> @@ -28,6 +28,7 @@ static const struct cpuid_bit cpuid_bits[] = { >> { X86_FEATURE_HW_PSTATE, CPUID_EDX, 7, 0x80000007, 0 }, >> { X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 }, >> { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 }, >> + { X86_FEATURE_AMD_PRED_CMD, CPUID_EBX, 12, 0x80000008, 0 }, > I replied to the previous version, but I'll add it here, too. > > This should be moved to the existing 0x80000008/EBX entry rather than have > it in scattered. > > Also, there will be a total of three bits: > IBPB: 0x80000008 EBX[12] > IBRS: 0x80000008 EBX[14] > STIBP: 0x80000008 EBX[15] > > Since IBRS and STIBP share the same MSR, if a processor only supports > STIBP (MSR bit 1), for ease of software implementation the processor > does not GP fault attempts to write bit 0. In a similar manner, if a > processor only suppors IBRS (MSR bit 0), the processor does not GP > fault attempts to write bit 1. Are you able to comment on the read behaviour after a write which is ignored? If the behaviour is "read as written" then virt cases are fine.  If the "ignore" causes a zero to be read back, then we're still going to need to intercept and emulate all VM accesses. Thanks, ~Andrew