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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84edc2d6dd3sm3283510b3a.46.2026.08.03.00.14.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 03 Aug 2026 00:14:16 -0700 (PDT) Message-ID: Date: Mon, 3 Aug 2026 15:14:11 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] clk: qcom: ipq-cmn-pll: keep the CMN block bus clocks enabled To: Stanislaw Pal , Bjorn Andersson , Stephen Boyd , Michael Turquette Cc: Brian Masney , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org, devnull+george.moussalem.outlook.com@kernel.org References: <20260730191353.557494-1-kuncy7@gmail.com> Content-Language: en-US From: Jie Luo In-Reply-To: <20260730191353.557494-1-kuncy7@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: zuDqnG_fEPKmYfaOGQhp7YobUkFysECQ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODAzMDA2MiBTYWx0ZWRfX8wBiRnw9imC7 Aoz+ra27iMjh1VBAG/FH9B4wJDFVSN++dnuzB7gI6xMjIFyJDRU+zGwSz/rm3aOB8VMDpSPQF1s uY3wkALC7ngJiZVqC9IMZ9mRioFQ0HiYX+LSpgIvKNJCPUtgvuT4hBnOMbXxDg95ToZ9lvQkro6 nbNWwqIdrQ7M1ZAQtagWkV5vj5/YQO0DwAHNAO8C+u6Sc14ZbrwEMvD++usTq2T2OrEiDNIHL1j ulM7a98+/Mz//FplIY08gecNZgrogteYeDaFDgG2IXfFV9cE4Yhgnx8GKl7TvLphiRlKNoxU3I8 EBzshdjIK1sn0WBU2U8iH6COXs8icZ0WcGKi/+u2V46eoNyZa9ih9GIZGEWJWd3FwgUXl6nJE9P N06CuZ6R85TPnDDwa4S4vzLqRTILdLeU8uFdDY9QKwLxr8Gv4Wz5rvKOo0dmTcCkpl+oUvHxDPH Xud0vjdjghzTiJAaOxQ== X-Proofpoint-GUID: zuDqnG_fEPKmYfaOGQhp7YobUkFysECQ X-Authority-Analysis: v=2.4 cv=PqSjqQM3 c=1 sm=1 tr=0 ts=6a703fca cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=VwQbUJbxAAAA:8 a=pGLkceISAAAA:8 a=7_mjQ7ShsriNIxc-HisA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwODAzMDA2MiBTYWx0ZWRfX//ufqmFFgf4L Xi195rZXPnTa41+6i05vGL015KsawhXRUNJOLwzzEfTaZZv6jZaarxJmjHOYor2TsjULb5QCwUw Qc6d8ZLZI8rVUmCZVVMPU3lbarCeaYU= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-02_06,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 phishscore=0 spamscore=0 priorityscore=1501 adultscore=0 clxscore=1015 impostorscore=0 suspectscore=0 bulkscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608030062 On 7/31/2026 3:13 AM, Stanislaw Pal wrote: > The probe function takes a runtime PM reference to enable the GCC AHB & > SYS clocks of the CMN PLL block, registers the clocks, and then drops > the reference. Once the autosuspend kicks in, pm_clk gates both clocks > a few milliseconds after probe has returned. > > That is wrong on two counts: > > - The clock ops access the CMN PLL registers without taking a runtime > PM reference of their own, so any later clk_set_rate() or rate > recalculation touches the register file with its bus clock gated. clk_cmn_pll_set_rate() is invoked as part of the AHB and SYS clock enable sequence. The CMN PLL clock rate is configured according to the DTS assigned-clock-rates-u64 property, which is applied when devm_of_clk_add_hw_provider() (called inside ipq_cmn_pll_register_clks()) triggers the call chain: of_clk_add_hw_provider() → of_clk_set_defaults() This corresponds to the following DTS entries: assigned-clocks = <&cmn_pll IPQ5018_CMN_PLL_CLK>; assigned-clock-rates-u64 = /bits/ 64 <4800000000>; > > - On IPQ5018 the consequences are not contained to this device: > gating the CMN block bus clocks makes the SoC hang on a subsequent > bus access. Measured on a TP-Link Archer AX55 v1 (IPQ5018), the > machine dies silently within a few milliseconds of the CMN PLL > probe returning - mid-character on the UART - and the victim is > whichever device happens to probe next. Whether a given boot > survives the window is a micro-timing lottery: different binary > layouts of the same kernel ranged from occasional failures to a > 100% reproducible boot loop. > > Keep the runtime PM usage count elevated on the probe success path, so > the bus clocks stay enabled. With this one change the same board went > from boot-looping to surviving every boot attempt (verified across > three previously-failing kernel binaries, plus repeated soft and hard > resets on the final one). The CMN PLL AHB/SYS clocks will remain enabled as long as a downstream consumer of the CMN PLL clocks is active — this behaviour was confirmed experimentally on the IPQ9574 platform as example. # insmod ipq-cmn-pll.ko # # devmem 0x9b780 0x00000000 # # insmod nsscc-ipq9574.ko # devmem 0x9b780 0x000000FF # > > Fixes: f81715a4c87c ("clk: qcom: Add CMN PLL clock controller driver for IPQ SoC") > Cc: stable@vger.kernel.org > Signed-off-by: Stanislaw Pal > --- > One more observation from the same debugging session, for the people > who know this silicon: on IPQ5018 the CMN_PLL_LOCKED bit (offset 0x64, > bit 8) never asserts. Every clk_cmn_pll_set_rate() call runs its > regmap_read_poll_timeout() to the full 100 ms timeout - including under > the bootloader-programmed configuration the hardware demonstrably runs > fine with - and nobody notices, because clk_change_rate() ignores the > .set_rate return value, so the -ETIMEDOUT is swallowed silently. Is the > lock status readable at a different offset on this SoC, or is the bit > simply not functional there? Happy to send a follow-up (surfacing the > error, or skipping the poll where it cannot work) once someone can say > what the intended behavior is. The CMN_PLL_LOCKED bit offset and behavior are consistent across all IPQ platforms — the same register layout applies to IPQ5018. > > drivers/clk/qcom/ipq-cmn-pll.c | 12 ++++++++++-- > 1 file changed, 10 insertions(+), 2 deletions(-) > > --- a/drivers/clk/qcom/ipq-cmn-pll.c > +++ b/drivers/clk/qcom/ipq-cmn-pll.c > @@ -454,11 +454,19 @@ > > /* Register CMN PLL clock and fixed rate output clocks. */ > ret = ipq_cmn_pll_register_clks(pdev); > - pm_runtime_put(dev); > - if (ret) > + if (ret) { > + pm_runtime_put(dev); > return dev_err_probe(dev, ret, > "Failed to register CMN PLL clocks\n"); > + } > > + /* > + * Keep the runtime PM usage count elevated on the success path, so > + * the CMN block AHB & SYS clocks stay enabled: the clock ops access > + * the CMN PLL registers without taking a runtime PM reference, and > + * on IPQ5018 gating these clocks after probe hangs the SoC on a > + * subsequent bus access. > + */ > return 0; > } > >