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Mon, 02 Sep 2024 07:24:20 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4827OIIB032617 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 2 Sep 2024 07:24:18 GMT Received: from [10.239.133.242] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 2 Sep 2024 00:24:15 -0700 Message-ID: Date: Mon, 2 Sep 2024 15:24:13 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 1/7] dt-bindings: arm: Add support for Coresight TGU trace To: Krzysztof Kozlowski , Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , References: <20240830092311.14400-1-quic_songchai@quicinc.com> <20240830092311.14400-2-quic_songchai@quicinc.com> <0a79b9df-4ca4-4dc8-9930-3fa1dc7d3174@kernel.org> <65732921-988f-41f7-886e-94415b07608e@quicinc.com> Content-Language: en-US From: songchai In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: bp2m_hFYMZ2_uBvHKLGYyn5UjYqk803H X-Proofpoint-ORIG-GUID: bp2m_hFYMZ2_uBvHKLGYyn5UjYqk803H X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-09-01_06,2024-08-30_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 mlxlogscore=999 spamscore=0 impostorscore=0 lowpriorityscore=0 suspectscore=0 phishscore=0 adultscore=0 priorityscore=1501 clxscore=1015 mlxscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2409020060 On 9/2/2024 3:02 PM, Krzysztof Kozlowski wrote: > On 02/09/2024 05:14, songchai wrote: >> On 8/30/2024 6:11 PM, Krzysztof Kozlowski wrote: >>> On 30/08/2024 11:23, songchai wrote: >>>> The Trigger Generation Unit (TGU) is designed to detect patterns or >>>> sequences within a specific region of the System on Chip (SoC). Once >>>> configured and activated, it monitors sense inputs and can detect a >>>> pre-programmed state or sequence across clock cycles, subsequently >>>> producing a trigger. >>>> >>>> TGU configuration space >>>> offset table >>>> x-------------------------x >>>> | | >>>> | | >>>> | | Step configuration >>>> | | space layout >>>> | coresight management | x-------------x >>>> | registers | |---> | | >>>> | | | | reserve | >>>> | | | | | >>>> |-------------------------| | |-------------| >>>> | | | | prioroty[3] | >>>> | step[7] |<-- | |-------------| >>>> |-------------------------| | | | prioroty[2] | >>>> | | | | |-------------| >>>> | ... | |Steps region | | prioroty[1] | >>>> | | | | |-------------| >>>> |-------------------------| | | | prioroty[0] | >>>> | |<-- | |-------------| >>>> | step[0] |--------------------> | | >>>> |-------------------------| | condition | >>>> | | | | >>>> | control and status | x-------------x >>>> | space | | | >>>> x-------------------------x |Timer/Counter| >>>> | | >>>> x-------------x >>>> TGU Configuration in Hardware >>>> >>>> The TGU provides a step region for user configuration, similar >>>> to a flow chart. Each step region consists of three register clusters: >>>> >>>> 1.Priority Region: Sets the required signals with priority. >>>> 2.Condition Region: Defines specific requirements (e.g., signal A >>>> reaches three times) and the subsequent action once the requirement is >>>> met. >>>> 3.Timer/Counter (Optional): Provides timing or counting functionality. >>>> >>>> Add a new coresight-tgu.yaml file to describe the bindings required to >>>> define the TGU in the device trees. >>>> >>>> Signed-off-by: songchai >>> It feels like you are using login name as real name. Please investigate >>> this and confirm whether latin transcription/transliteration of your >>> name is like above. >> yes.. it's my login name. Will use my real name in next version. >>>> --- >>>> .../bindings/arm/qcom,coresight-tgu.yaml | 136 ++++++++++++++++++ >>>> 1 file changed, 136 insertions(+) >>>> create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-tgu.yaml >>>> >>>> diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tgu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tgu.yaml >>>> new file mode 100644 >>>> index 000000000000..c261252e33e0 >>>> --- /dev/null >>>> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tgu.yaml >>>> @@ -0,0 +1,136 @@ >>>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >>>> +# Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. >>>> +%YAML 1.2 >>>> +--- >>>> +$id:http://devicetree.org/schemas/arm/qcom,coresight-tgu.yaml# >>>> +$schema:http://devicetree.org/meta-schemas/core.yaml# >>>> + >>>> +title: Trigger Generation Unit - TGU >>>> + >>>> +description: | >>>> + The Trigger Generation Unit (TGU) is a Data Engine which can be utilized >>>> + to sense a plurality of signals and create a trigger into the CTI or >>>> + generate interrupts to processors. The TGU is like the trigger circuit >>>> + of a Logic Analyzer.The corresponding trigger logic can be realized by >>>> + configuring the conditions for each step after sensing the signal. >>>> + Once setup and enabled, it will observe sense inputs and based upon >>>> + the activity of those inputs, even over clock cycles, may detect a >>>> + preprogrammed state/sequence and then produce a trigger or interrupt. >>>> + >>>> + The primary use case of the TGU is to detect patterns or sequences on a >>>> + given set of signals within some region of the SoC. >>>> + >>>> +maintainers: >>>> + - Mao Jinlong >>>> + - Sam Chai >>>> + >>>> +# Need a custom select here or 'arm,primecell' will match on lots of nodes >>>> +select: >>>> + properties: >>>> + compatible: >>>> + contains: >>>> + enum: >>>> + - qcom,coresight-tgu >>>> + required: >>>> + - compatible >>>> + >>>> +properties: >>>> + $nodename: >>>> + pattern: "^tgu(@[0-9a-f]+)$" >>> Drop the pattern (and anyway @ is not optional). >> There will be several TGUs in the SoC, and we want to use the address of >> each to distinguish them. > How is this related? > >> This is why we added the nodename pattern here. > How is this related? > >> Additionally, I noticed that both TPDM and CTI also use this format to >> define the nodename. >> >> Could you please share any concerns you have about using this pattern? > I don't get why you insist, but sure: > The name does not follow DT spec recommendation, plus child schema is > not really supposed to define the names. Thanks for you clarification, will drop in the next version. > >>>> + compatible: >>>> + items: >>>> + - const: qcom,coresight-tgu >>>> + - const: arm,primecell >>>> + >>>> + reg: >>>> + maxItems: 1 >>>> + >>>> + clocks: >>>> + maxItems: 1 >>>> + >>>> + clock-names: >>>> + items: >>>> + - const: apb_pclk >>>> + >>>> + qcom,tgu-steps: >>>> + description: >>>> + The trigger logic is realized by configuring each step after sensing >>>> + the signal. The parameter here is used to describe the maximum of steps >>>> + that could be configured in the current TGU. >>> Why this is board or SoC level property? All below also feel like >>> unnecessary stuff from downstream. >> There are actually four properties used to describe the number of >> registers with different functionality for TGUs at the SoC level. >> >> Each TGU may have a different number of registers, so we need to add >> these four properties to describe each TGU’s hardware design. > Each TGU on the same SoC? yes, in other words, there will be several TGUs in the SoC. > > > > Best regards, > Krzysztof >