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bh=rZCTxMdK6MZjjpQW3uDf8zn3t6KnbdfVhR/xoMax9cY=; b=Mh8kymApd0YspXD/EJ88D/anKMwSwIetKzA5hvv1vKwneiM9AO/5uEr6 8EncghO0+zEkl7GjyQI9PNWhVU0KzlhUGaiLmzVVmIuevR43++ChrzWK8 5EXUm+0S0kAqmdRZMiGiEcGdfcoNslS5WEdjcPEBh9hTE7OpDGM0p3kGR kP0aRCnaekmW1YdpZ1lIVk1PpW/WdFS/vVOIT5mrq2J+Ch5R8XQBStHvN unbF85Nk0oTflsS00UckC8kZPrbWVTMhYWpC2kn/LCwIyf570BaOqFjZ+ AETng3SdjmWkgnnaXy2H3H7OzgOzLbs7u//DomZHrKZVPEuGMu99ATdJY Q==; X-CSE-ConnectionGUID: V12xdO4iREeHjZSvkPYvIQ== X-CSE-MsgGUID: klZk0XvERU+ANt6YON9MwQ== X-IronPort-AV: E=Sophos;i="6.08,201,1712613600"; d="scan'208";a="37143700" Received: from vmailcow01.tq-net.de ([10.150.86.48]) by mx1.tq-group.com with ESMTP; 30 May 2024 13:36:15 +0200 Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 450BE166314; Thu, 30 May 2024 13:36:11 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ew.tq-group.com; s=dkim; t=1717068971; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=rZCTxMdK6MZjjpQW3uDf8zn3t6KnbdfVhR/xoMax9cY=; b=rQgiANPF7tbt23kQzGSgR3ZJcprOX8jC1tT64aPC4T06VmuSb6lhKLmtHfNU8Hd/j4xluZ 0icNYtF0K6zCj+Q49qY+A6mxidyieT8rMutQEcQcYckVhjelUCEwLXuBYn8z6XA2vsMMj4 cnV8m+YKDykzNMbBJz1ltv4eZ3GuCCOUzS2o0K1ncvhhKN0YPK9gQtQNbh0iqqBQQnhpxw qfuT9kIKg6iLGSqWlsf21/9jTT6IES29uxfbKaUEB3ZviSmzuABK1tAmadfsf1abXSXEBc dwlK2Lg9LkuoRdION47fU1BdmzKPH6zj2aWQEiz9GdlylMKdUYjR686Gp0IIMA== Message-ID: Subject: Re: [PATCH 8/8] gpio: tqmx86: fix broken IRQ_TYPE_EDGE_BOTH interrupt type From: Matthias Schiffer To: Dan Carpenter Cc: Linus Walleij , Bartosz Golaszewski , Andrew Lunn , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Gregor Herburger , linux@ew.tq-group.com Date: Thu, 30 May 2024 13:36:10 +0200 In-Reply-To: References: <2c265b6bcfcde7d2327b94c4f6e3ad6d4f1e2de7.1716967982.git.matthias.schiffer@ew.tq-group.com> <8689fbcd-3fa3-410b-8fc9-7a699bf163b8@moroto.mountain> <0e971f0b885bd360e33ef472d96e3d9e0ab56405.camel@ew.tq-group.com> <876eb824-2898-4ffe-9d0e-69dd0781729f@moroto.mountain> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.44.4-0ubuntu2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 On Thu, 2024-05-30 at 13:15 +0200, Matthias Schiffer wrote: > On Thu, 2024-05-30 at 13:22 +0300, Dan Carpenter wrote: > >=20 > > On Thu, May 30, 2024 at 10:39:25AM +0200, Matthias Schiffer wrote: > > > On Wed, 2024-05-29 at 17:38 +0300, Dan Carpenter wrote: > > > >=20 > > > > On Wed, May 29, 2024 at 09:45:20AM +0200, Matthias Schiffer wrote: > > > > > diff --git a/drivers/gpio/gpio-tqmx86.c b/drivers/gpio/gpio-tqmx8= 6.c > > > > > index c957be3341774..400415676ad5d 100644 > > > > > --- a/drivers/gpio/gpio-tqmx86.c > > > > > +++ b/drivers/gpio/gpio-tqmx86.c > > > > > @@ -126,9 +126,15 @@ static void _tqmx86_gpio_irq_config(struct t= qmx86_gpio_data *gpio, int hwirq) > > > > > unsigned int offset =3D hwirq - TQMX86_NGPO; > > > > > u8 type =3D TQMX86_INT_TRIG_NONE, mask, val; > > > > > =20 > > > > > - if (gpio->irq_type[hwirq] & TQMX86_INT_UNMASKED) > > > > > + if (gpio->irq_type[hwirq] & TQMX86_INT_UNMASKED) { > > > > > type =3D gpio->irq_type[hwirq] & TQMX86_INT_TRIG_MASK; > > > > > =20 > > > > > + if (type =3D=3D TQMX86_INT_TRIG_BOTH) > > > > > + type =3D tqmx86_gpio_get(&gpio->chip, hwirq) > > > > ^^^^^ > > > >=20 > > > > > + ? TQMX86_INT_TRIG_FALLING > > > > > + : TQMX86_INT_TRIG_RISING; > > > > > + } > > > > > + > > > > > mask =3D TQMX86_GPII_MASK(offset); > > > > ^^^^^^ > > > > > val =3D TQMX86_GPII_CONFIG(offset, type); > > > > ^^^^^^ > > > > > _tqmx86_gpio_update_bits(gpio, TQMX86_GPIIC, mask, val); > > > >=20 > > > > The offset stuff wasn't beautiful and I'm glad you are deleting it.= My > > > > understanding is that a hwirq is 0-3 for output or 4-7 input. An o= ffset > > > > is "hwirq % 4"? > > > >=20 > > > > There are a bunch of places which are still marked as taking an off= set > > > > but they all actually take a hwirq. For example, tqmx86_gpio_get() > > > > above. The only things which still actually take an offset are the > > > > TQMX86_GPII_MASK() and TQMX86_GPII_CONFIG() macros. > > > >=20 > > > > Could you: > > > > 1) Modify TQMX86_GPII_MASK() and TQMX86_GPII_CONFIG() to take a hwi= rq? > > > > 2) Rename all the "offset" variables to "hwirq"? > > >=20 > > > Unfortunately, the TQMx86 GPIO is a huge mess, and the mapping betwee= n GPIO numbers and IRQ numbers > > > depends on the hardware generation/variant. I don't think it is possi= ble to have GPIO numbers and > > > hwirq numbers differ, is it? > > >=20 > > > Currently, the driver only supports COM Express modules, where IRQs 0= -3 correspond to GPIOs 4-7, > > > while GPIOs 0-3 don't have interrupt support. > >=20 > > I'm so confused. > >=20 > > So "offset" is the GPIO number and "hwirq" is the IRQ number? If the > > IRQ numbers are 0-3 then why do we subtract 4 to get the GPIO number in >=20 > The current naming in the driver is confusing and I'll fix that in the ne= xt round of refactoring > patches. >=20 > Generally, hwirq =3D=3D GPIO number (I have not found a way to change thi= s mapping - if there is one, > I'd be interested to try if it makes the code less confusing). "offset" c= urrently always refers to > some shift in a hardware register. In tqmx86_gpio_get and tqmx86_gpio_set= , offset is a GPIO number. > In all functions dealing with IRQs, offset is an IRQ number (which is dif= ferent from the hwirq > number). >=20 > Matthias Ah, I just noticed the "to_irq" function in struct gpio_chip, I guess I sim= ply didn't look in the right place before. Will have a closer look when I rebase the refactoring p= atches. Matthias >=20 >=20 > > _tqmx86_gpio_irq_config()? > >=20 > > unsigned int offset =3D hwirq - TQMX86_NGPO; > >=20 > > And again, it's just weird to call: > >=20 > > type =3D tqmx86_gpio_get(&gpio->chip, hwirq); > >=20 > > where we're passing "hwirq" when tqmx86_gpio_get() takes an "offset" as > > an argument. > >=20 > > regards, > > dan carpenter > >=20 >=20 --=20 TQ-Systems GmbH | M=C3=BChlstra=C3=9Fe 2, Gut Delling | 82229 Seefeld, Germ= any Amtsgericht M=C3=BCnchen, HRB 105018 Gesch=C3=A4ftsf=C3=BChrer: Detlef Schneider, R=C3=BCdiger Stahl, Stefan Sch= neider https://www.tq-group.com/