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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2e53a4a80c7sm27395199eec.10.2026.04.21.23.19.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Apr 2026 23:19:26 -0700 (PDT) Date: Tue, 21 Apr 2026 23:19:24 -0700 From: Qiang Yu To: Krzysztof Kozlowski Cc: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 1/5] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add support for glymur Gen5 x8 bifurcation mode Message-ID: References: <20260412-glymur_gen5x8_phy_0413-v3-0-affcebc16b8b@oss.qualcomm.com> <20260412-glymur_gen5x8_phy_0413-v3-1-affcebc16b8b@oss.qualcomm.com> <20260415-wooden-prawn-of-lightning-dc1ddc@quoll> <20260417-awesome-tacky-coot-e59a30@quoll> <20260420-optimistic-unnatural-stingray-80da35@quoll> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260420-optimistic-unnatural-stingray-80da35@quoll> X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDIyMDA1NyBTYWx0ZWRfX7eVOOSmzsSJD CoBvXsfWdYWcAvWt7zo9puOa9cCKZW0M/zhhWLTh4qxIq5rKA2wKZcXzQ/+sm/xn6CNNExpFSOz sAtkNAGBrI8s1OkRa383NeNzPHjybdj9AKSNt/nVHxU/DR0U00UJC0g95Xt2qcwThvuL7iW4DJl v4SOF0tFSQm8vRnBT8ktc8sfZGNZpLWXRfmJMfzEw9Cte/0Sk+iU2LlgiczFojnSlM2y1ForWFL aXNOyQWwSEmFxmnnpjpqvtNHwFnC0yiD5QQBMC3NExDNQ1gsoRKLpgYr0iMJCzD/Qn4eoM5iomR rjgxQzgvIUJ72Ro72GpygvbFRoCuHKcArkCcUv87r9BG6fWm0VaSh7zbI2xyEriTyG1q9CjKVTi 1W8dZ5po6RxKXK49c5sYH1SS/DrSH4unVMw1Yar9aR0P3gt9sHnr7p1t2NpSR8t9I4Qrad1L7Sf 5Pw6arBDyoLNwXmv6Mw== X-Proofpoint-GUID: AYk6BaUI1KIGlwXF1PnioVSR_6bOqvwO X-Proofpoint-ORIG-GUID: AYk6BaUI1KIGlwXF1PnioVSR_6bOqvwO X-Authority-Analysis: v=2.4 cv=RoT16imK c=1 sm=1 tr=0 ts=69e86870 cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=kj9zAlcOel0A:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=TH_F0qHjsvcmixwPkT0A:9 a=CjuIK1q_8ugA:10 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-21_03,2026-04-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 impostorscore=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 adultscore=0 bulkscore=0 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604220057 On Mon, Apr 20, 2026 at 03:23:43PM +0200, Krzysztof Kozlowski wrote: > On Mon, Apr 20, 2026 at 12:23:19AM -0700, Qiang Yu wrote: > > On Fri, Apr 17, 2026 at 11:18:08AM +0200, Krzysztof Kozlowski wrote: > > > On Wed, Apr 15, 2026 at 07:58:13PM -0700, Qiang Yu wrote: > > > > On Wed, Apr 15, 2026 at 09:50:28AM +0200, Krzysztof Kozlowski wrote: > > > > > On Sun, Apr 12, 2026 at 11:25:56PM -0700, Qiang Yu wrote: > > > > > > The Glymur SoC has pcie3a and pcie3b PHYs that can operate in two modes: > > > > > > > > > > > > 1. Independent 4-lane mode: Each PHY operates as a separate PCIe Gen5 > > > > > > 4-lane interface, compatible with qcom,glymur-qmp-gen5x4-pcie-phy > > > > > > 2. Bifurcation mode (8-lane): pcie3a phy acts as leader and pcie3b phy as > > > > > > follower to form a single 8-lane PCIe Gen5 interface > > > > > > > > > > > > In bifurcation mode, the hardware design requires controlling additional > > > > > > resources beyond the standard pcie3a PHY configuration: > > > > > > > > > > > > - pcie3b's aux_clk (phy_b_aux) > > > > > > - pcie3b's phy_gdsc power domain > > > > > > - pcie3b's bcr/nocsr reset > > > > > > > > > > > > Add qcom,glymur-qmp-gen5x8-pcie-phy compatible string to document this > > > > > > 8-lane bifurcation configuration. > > > > > > > > > > Do you describe PCI3A or PCI3B or something combined PCI3? > > > > > > > > I describe a single x8 PHY with resources from both the pcie3a and pcie3b > > > > PHY blocks for x8 operation. > > > > > > > > > > > > > > > > > > > > > The phy_b_aux clock is used as the 6th clock instead of pipediv2, > > > > > > requiring the clock-names enum to be extended to support both > > > > > > [phy_b_aux, pipediv2] options at index 5. This follows the existing > > > > > > pattern used for [rchng, refgen] clocks at index 3. > > > > > > > > > > > > Signed-off-by: Qiang Yu > > > > > > --- > > > > > > .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 53 ++++++++++++++++++---- > > > > > > 1 file changed, 45 insertions(+), 8 deletions(-) > > > > > > > > > > > > diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml > > > > > > index 3a35120a77ec0ceb814a1cdcacff32fef32b4f7b..14eba5d705b1956c1bb00cc8c95171ed6488299b 100644 > > > > > > --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml > > > > > > +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml > > > > > > @@ -18,6 +18,7 @@ properties: > > > > > > enum: > > > > > > - qcom,glymur-qmp-gen4x2-pcie-phy > > > > > > - qcom,glymur-qmp-gen5x4-pcie-phy > > > > > > + - qcom,glymur-qmp-gen5x8-pcie-phy > > > > > > > > > > That's the same device as 5x4, no? One device, one compatible and this > > > > > suggests you will have three PCI phys in the DT - two 5x4 and one 5x8? > > > > > > > > > > > > > It is not the same as the 5x4 PHY. In DT, we model three PHY nodes: > > > > phy_3a (1x4), phy_3b (1x4), and a separate phy_1x8 node for x8 mode. > > > > > > OK, that's what I wanted to hear. And that's what should not be done, > > > > > > You should not have a separate node for the same hardware. First, DTC > > > will give you a W=1 warning, although warning itself should be moved to > > > W=2. > > > > > > Second, the warning tells important story - same hardware is described > > > twice. > > > > > > You only need phy_3a and phy_3b, so only two in total. > > > > We can keep only phy_3a and phy_3b, but still add new compatible > > qcom,glymur-qmp-gen5x8-pcie-phy in binding, right? > > > > For boards that support pcie3a(1x4) + pcie3b(1x4), DTS would be: > > > > pcie3a_phy { compatible = "qcom,glymur-qmp-gen5x4-pcie-phy"; }; > > pcie3b_phy { compatible = "qcom,glymur-qmp-gen5x4-pcie-phy"; }; > > > > For boards that support 1x8, we would override pcie3a_phy with: > > > > pcie3a_phy { compatible = "qcom,glymur-qmp-gen5x8-pcie-phy"; /* additional resources */ }; > > pcie3b_phy { compatible = "qcom,glymur-qmp-gen5x4-pcie-phy"; }; > > > > This still uses only two PHY nodes and DTC will not report warning. > > IMO, you do not need another compatible. Device is exactly the same. If > wiring on the board differs, e.g. you have 8x instead of 4x, you: > 1. disable unused 3B phy. > 2. Add to 3A missing resources or the phandle to companion node. > > At least that is what I tought till now, when I opened the HPG/manual > for Glymur phy. Someone skipped important information when PCIe PHY was > upstreamed first and glymur.dtsi already got PHY 3B described. > > Reminder: writing bindings asks you explicitly to post COMPLETE > bindings. > > If you posted COMPLETE bindings we would question all this and you would > have to check in user manual that this is actually ONE device. > > There is no 5x4 phy 3A and 3B, at least HPG is pretty clear here. PHY_A and PHY_B are two sub PHYs that can act independently. I thought we can describe them. And for previous target eg Hamoa, we also descibed like this. > > And you should start with that. > > But you posted first incomplete binding, hiding the rest and now you > have 5x4 merged into DTSI. > > So let's rephrase based on manual: > You have only one PCIE phy3. Not 3A + 3B. That one phy3 can be > configured by consumers (board) differently, e.g. by requesting 8-lane > or twice 4-lane phys. > > Let me send correction note for glymur.dtsi. > So we can have only one compatible "qcom,glymur-qmp-gen5x8-pcie-phy" and one phy dts node? - Qiang Yu > Best regards, > Krzysztof >