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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2e53ac84c38sm26929968eec.13.2026.04.22.23.29.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Apr 2026 23:29:49 -0700 (PDT) Date: Wed, 22 Apr 2026 23:29:47 -0700 From: Qiang Yu To: Krzysztof Kozlowski Cc: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 1/5] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add support for glymur Gen5 x8 bifurcation mode Message-ID: References: <20260412-glymur_gen5x8_phy_0413-v3-0-affcebc16b8b@oss.qualcomm.com> <20260412-glymur_gen5x8_phy_0413-v3-1-affcebc16b8b@oss.qualcomm.com> <20260415-wooden-prawn-of-lightning-dc1ddc@quoll> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Proofpoint-ORIG-GUID: oLBh3toK5xma5Awf7Tzh_-IHCDu0nati X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDIzMDA1OSBTYWx0ZWRfX+rr/KjdsEozt Ag4Sg8l2ldcjUPucl66XQWENjKg8hXiH1q3+nY1KUbLgBYROCuitWTKtiGbLI0Al4eJkf/HxxwZ onzCPpBmUbGDOLYYDcYt/D47bBpMh8yf87ZxvOj4U4MIjlW1IHuEWc48M7ZqHrf/JJ8ks40B/Y2 yUQgjGXz6+UuwUFOYXG3LR6E7JzWq6X3evxcTVV0PBWccgvKq13vbalnmIpi/NH8ayCvEnxvI/q 0yJ2ATwkAvWZ4ZmUA8mlcmpoLt3DS91oeoF4G29oopq2d+nTHUE0d7sMqQgDILt8ybpxLlBT2mi hyH6ChWfxKg++2d337hD8oQlME/tzNx0g1fpToh8ZaArpuM9TkU/M9Uw+9TYzZv8qbkHtrTyDbh fq/O57d2rzVEG9AKj6TNmA1Wj1K1jCYvahP0jm4Rw+fTzj2GZkHjr6c5sloLZcwRiRmyP4brT52 WqHoHKZKxY+gjvyAcQQ== X-Authority-Analysis: v=2.4 cv=PsOjqQM3 c=1 sm=1 tr=0 ts=69e9bc5e cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=kj9zAlcOel0A:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=sVFJkvLo0iv11KXttJkA:9 a=CjuIK1q_8ugA:10 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-GUID: oLBh3toK5xma5Awf7Tzh_-IHCDu0nati X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-23_01,2026-04-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 phishscore=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 clxscore=1015 bulkscore=0 malwarescore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604230059 On Wed, Apr 22, 2026 at 08:27:02AM +0200, Krzysztof Kozlowski wrote: > On 16/04/2026 04:58, Qiang Yu wrote: > >>> reset-names: > >>> minItems: 1 > >>> items: > >>> - const: phy > >>> - const: phy_nocsr > >>> + - const: phy_b > >>> + - const: phy_b_nocsr > >> > >> And now I doubt that all the changes here are for duplicated node. > >> > > > > All the changes here are for 1x8 PHY node. > > > >> Maybe just the commit msg is confusing and instead of describing some > >> node which combines two other phys just say what device is here being > >> described. > >> > > > > Okay, I will focus on describing the required resources. Is the > > description below clearer? > > > > Glymur has two physical Gen5x4 PCIe PHY blocks: pcie3a phy and pcie3b phy. > > > I just proven you that it is not true. > Yeah, I see it. I have to say you are right. It is a 1x8 PHY. We can set the phy-cell to 1 and controller driver use different args to determine it requires 1x4_a, 1x4_b or 1x8. - Qiang Yu > Best regards, > Krzysztof