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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Oct 2024 09:50:27.4059 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5bd763e0-7659-4d6b-aaa2-08dcecfecc5e X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DU6PEPF0000A7E3.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB9361 On 04/10/2024 15:43, Steven Price wrote: > When __change_memory_common() is purely setting the valid bit on a PTE > (e.g. via the set_memory_valid() call) there is no need for a TLBI as > either the entry isn't changing (the valid bit was already set) or the > entry was invalid and so should not have been cached in the TLB. > > Reviewed-by: Catalin Marinas > Signed-off-by: Steven Price Reviewed-by: Suzuki K Poulose > --- > v4: New patch > --- > arch/arm64/mm/pageattr.c | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/mm/pageattr.c b/arch/arm64/mm/pageattr.c > index 0e270a1c51e6..547a9e0b46c2 100644 > --- a/arch/arm64/mm/pageattr.c > +++ b/arch/arm64/mm/pageattr.c > @@ -60,7 +60,13 @@ static int __change_memory_common(unsigned long start, unsigned long size, > ret = apply_to_page_range(&init_mm, start, size, change_page_range, > &data); > > - flush_tlb_kernel_range(start, start + size); > + /* > + * If the memory is being made valid without changing any other bits > + * then a TLBI isn't required as a non-valid entry cannot be cached in > + * the TLB. > + */ > + if (pgprot_val(set_mask) != PTE_VALID || pgprot_val(clear_mask)) > + flush_tlb_kernel_range(start, start + size); > return ret; > } >