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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 9KibNGlIKy0jMR1qri51l/b8qcd8/sj64duVhbGQKj8194cBobmVJlONyGOTwmgpn9zUgcrOOPmdX7eV5EmfZ62AejGvMQADQfcrP9EMbMR2FJ5oeyBvImyUI06J2YSgkYz6DRTXHF+CNBESuqK3CmOfyQvLIMT5nMQYEWT+cm2BTvZCxm9miGxTFEqQHYUJ1nILcBUvDNb+/2qoJZt39HndBJUUZ5DTeiCHdK5DMN1hoKVUgvR8YpSL+h2nFlP11gsONUggKGtglsmzqCsHPhYer4czwZC9aSmFXCKIorJr+tDhQtrOC6thidrW6aHcpcSglm9+wyM9KJbvVb0FJwq8vGLZaLbHcTAY2PFxFJhWz8DUxwS3RAel0EOoP8Jr/Ha7nOoIkClkmGOMBerm8sppv2HzrUGeowzzSRETZXkdw1who/F7evPuH9FoKouf X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Sep 2026 10:19:30.8956 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4cec1a41-0a89-461f-6818-08df1edc5105 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF0000A994.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6295 From: Peter Colberg Wrap pci_enable_sriov() and pci_disable_sriov() on Device for use by the SR-IOV callback tokens and their rollback guard. Keep these operations internal so drivers can only enable or disable VFs through the callback-scoped API introduced later in this series. Suggested-by: Danilo Krummrich Signed-off-by: Peter Colberg Signed-off-by: Zhi Wang --- rust/kernel/pci.rs | 2 ++ rust/kernel/pci/iov.rs | 46 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) create mode 100644 rust/kernel/pci/iov.rs diff --git a/rust/kernel/pci.rs b/rust/kernel/pci.rs index 3ec897709e89..b11a1d32c5db 100644 --- a/rust/kernel/pci.rs +++ b/rust/kernel/pci.rs @@ -34,6 +34,8 @@ mod id; mod io; +#[cfg(CONFIG_PCI_IOV)] +mod iov; mod irq; pub use self::id::{ diff --git a/rust/kernel/pci/iov.rs b/rust/kernel/pci/iov.rs new file mode 100644 index 000000000000..c37ce5134673 --- /dev/null +++ b/rust/kernel/pci/iov.rs @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! Abstractions for PCI Single Root I/O Virtualization (SR-IOV) drivers. + +use super::Device; + +use crate::{ + bindings, + device, + error::to_result, + prelude::*, // +}; + +impl Device> { + /// Enable the Single Root I/O Virtualization (SR-IOV) capability for this device, + /// where `nr_virtfn` is number of Virtual Functions (VF) to enable. + #[expect(dead_code)] + pub(crate) fn enable_sriov(&self, nr_virtfn: c_int) -> Result { + // SAFETY: + // `self.as_raw` returns a valid pointer to a `struct pci_dev`. + // + // `pci_enable_sriov()` checks that the enable operation is valid: + // - the device is a Physical Function (PF), + // - SR-IOV is currently disabled, and + // - `nr_virtfn` does not exceed the total number of supported VFs. + // + // The CoreInternal device context inherits from the Bound device context, + // which guarantees that the PF device is bound to a driver. + to_result(unsafe { bindings::pci_enable_sriov(self.as_raw(), nr_virtfn) }) + } + + /// Disable the Single Root I/O Virtualization (SR-IOV) capability for this device. + #[expect(dead_code)] + pub(crate) fn disable_sriov(&self) { + // SAFETY: + // `self.as_raw` returns a valid pointer to a `struct pci_dev`. + // + // `pci_disable_sriov()` checks that the disable operation is valid: + // - the device is a Physical Function (PF), and + // - SR-IOV is currently enabled. + // + // The CoreInternal device context inherits from the Bound device context, + // which guarantees that the PF device is bound to a driver. + unsafe { bindings::pci_disable_sriov(self.as_raw()) }; + } +} -- 2.53.0