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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-62fa5d4189bsm1616785a12.19.2025.09.18.08.38.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 18 Sep 2025 08:38:16 -0700 (PDT) Message-ID: Date: Thu, 18 Sep 2025 17:38:13 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC] dt-bindings: thunderbolt: Add Qualcomm USB4 Host Router To: Mika Westerberg Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Wesley Cheng , Jack Pham , Raghavendra Thoorpu , Dmitry Baryshkov , Mayank Rana , Krishna Kurapati , Manivannan Sadhasivam , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Andreas Noever , Mika Westerberg , Yehezkel Bernat , linux-usb@vger.kernel.org References: <20250916-topic-qcom_usb4_bindings-v1-1-943ecb2c0fa7@oss.qualcomm.com> <20250917061236.GF2912318@black.igk.intel.com> <20250918051244.GJ2912318@black.igk.intel.com> <035c0d66-bddd-495c-bd23-e1d98570ba7f@oss.qualcomm.com> <20250918152322.GK2912318@black.igk.intel.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250918152322.GK2912318@black.igk.intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTE2MDIwMiBTYWx0ZWRfXyiFO+n1X77iq ttMHBl9fmEV2EtExkBHzoTpYfVFZDhcC7MoRQFViBwTjhVcT8UH+XS+AuPuzXvQjumIT/pqTfzh eE3ZavhLIqc7fm3FAKUpuZrk/Xbp5OMVgVQHS95MoDrxsFXiMTtzLriSmUnsiJwSAG9EX6fXGgv p3lBZnbnxqq0FVany6zMEq/WH93iiyaePLkuAvmNxYmanungo4Ntz802rQsWJLa9XJuV6nK8eT0 BxI8ADXCLheyH8/9DJmUXVJapXLq1gb8UWkHP3mJfe/F8eSOV4E3OtiMjPIzK08WVuJtHiSxJ6j 2oRRnD3SyEEayY7LyTHkDewX7MD5OFxpnWKjsdBbfFdO9zjB0qUaKesQ/6dEAQOpdnE9m+wKFyN gdYA1fXt X-Proofpoint-ORIG-GUID: Lv7XkND7YMmEZjvruengrgz4d31BrI6t X-Authority-Analysis: v=2.4 cv=KJZaDEFo c=1 sm=1 tr=0 ts=68cc276a cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=Zu-_-z5cN0bD-gc8aucA:9 a=QEXdDO2ut3YA:10 a=a_PwQJl-kcHnX1M80qC6:22 X-Proofpoint-GUID: Lv7XkND7YMmEZjvruengrgz4d31BrI6t X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-18_01,2025-09-18_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 bulkscore=0 adultscore=0 impostorscore=0 suspectscore=0 malwarescore=0 clxscore=1015 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509160202 On 9/18/25 5:23 PM, Mika Westerberg wrote: > Hi, > > On Thu, Sep 18, 2025 at 11:05:42AM +0200, Konrad Dybcio wrote: >>> I it hard to change these DT bindings later on? If yes then I would >>> definitely think forward and make this support MSI from the get-go. >> >> dt-bindings (attempt to) promise an ABI-like interface, so bindings >> for *a given IP block* ("dt-bindings describe the hardware") should >> not change, unless there's something critically wrong (e.g. "this >> could have never really worked"). > > Then I think it is good to think few steps forward and make sure when > Qualcomm adds MSI to their IP it can be easily desribed in the DT bindings. Your reply makes me believe I glossed over an important detail.. If qcom,x1e80100-hr doesn't have MSIs, qcom,nextsoc-hr can add them without any issues too, just that the X1E80100 binding can't be altered, e.g. "binding" refers to the (compatible, allowed_props, required_props) tuple Konrad > >> Adding new properties is always OK, marking the new properties as >> 'required' is not (unless it falls into the aforementioned case). >> >> It's also totally OK to add MSI properties to e.g. Apple Host Router >> bindings specifically when they come around, as it's simply a different >> piece of hardware. It's also OK to create a usb4-host-router.yaml down >> the line, which will act as a common include and perform any >> maintenance/code churn, so long as it doesn't end up in the bindings >> for any specific hw block (e.g. this QC one) becoming more strict >> than they were on HEAD^. > > Okay thanks for the explanation.