From: Andrew Cooper <andrew.cooper3@citrix.com>
To: David Woodhouse <dwmw@amazon.co.uk>, Andi Kleen <ak@linux.intel.com>
Cc: Paul Turner <pjt@google.com>, LKML <linux-kernel@vger.kernel.org>,
Linus Torvalds <torvalds@linux-foundation.org>,
Greg Kroah-Hartman <gregkh@linux-foundation.org>,
Tim Chen <tim.c.chen@linux.intel.com>,
Dave Hansen <dave.hansen@intel.com>, <tglx@linutronix.de>,
Kees Cook <keescook@google.com>, Rik van Riel <riel@redhat.com>,
Peter Zijlstra <peterz@infradead.org>,
Andy Lutomirski <luto@amacapital.net>,
Jiri Kosina <jikos@kernel.org>, <gnomes@lxorguk.ukuu.org.uk>,
<x86@kernel.org>, <thomas.lendacky@amd.com>,
Josh Poimboeuf <jpoimboe@redhat.com>
Subject: Re: [PATCH] x86/retpoline: Fill RSB on context switch for affected CPUs
Date: Fri, 12 Jan 2018 18:05:36 +0000 [thread overview]
Message-ID: <af81cc6a-5d11-3066-1af3-7788384ad31e@citrix.com> (raw)
In-Reply-To: <1515779365-9032-1-git-send-email-dwmw@amazon.co.uk>
On 12/01/18 17:49, David Woodhouse wrote:
> When we context switch from a shallow call stack to a deeper one, as we
> 'ret' up the deeper side we may encounter RSB entries (predictions for
> where the 'ret' goes to) which were populated in userspace. This is
> problematic if we have neither SMEP nor KPTI (the latter of which marks
> userspace pages as NX for the kernel), as malicious code in userspace
> may then be executed speculatively. So overwrite the CPU's return
> prediction stack with calls which are predicted to return to an infinite
> loop, to "capture" speculation if this happens. This is required both
> for retpoline, and also in conjunction with IBRS for !SMEP && !KPTI.
>
> On Skylake+ the problem is slightly different, and an *underflow* of the
> RSB may cause errant branch predictions to occur. So there it's not so
> much overwrite, as *filling* the RSB to attempt to prevent it getting
> empty. This is only a partial solution for Skylake+ since there are many
> other conditions which may result in the RSB becoming empty. The full
> solution on Skylake+ is to use IBRS, which will prevent the problem even
> when the RSB becomes empty. With IBRS, the RSB-stuffing will not be
> required on context switch.
If you unconditionally fill the RSB on every entry to supervisor mode,
then there are never guest-controlled RSB values to be found.
With that property (and IBRS to protect Skylake+), you shouldn't need
RSB filling anywhere in the middle.
~Andrew
next prev parent reply other threads:[~2018-01-12 18:05 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-12 17:49 David Woodhouse
2018-01-12 18:02 ` Andi Kleen
2018-01-12 18:23 ` David Woodhouse
2018-01-12 18:05 ` Andrew Cooper [this message]
2018-01-12 18:56 ` David Woodhouse
2018-01-12 23:41 ` Josh Poimboeuf
2018-01-14 11:39 ` Thomas Gleixner
2018-01-14 17:04 ` [tip:x86/pti] " tip-bot for David Woodhouse
2018-01-15 14:35 ` David Laight
2018-01-15 14:39 ` David Woodhouse
2018-01-15 14:42 ` Arjan van de Ven
2018-01-15 20:03 ` Kees Cook
2018-01-14 23:37 ` tip-bot for David Woodhouse
2018-01-15 0:05 ` Andi Kleen
2018-01-15 0:09 ` Andi Kleen
2018-01-15 10:13 ` David Woodhouse
2018-03-09 13:12 ` Maciej S. Szmigiero
2018-03-09 15:14 ` Andi Kleen
2018-03-09 15:33 ` Maciej S. Szmigiero
2018-03-09 15:38 ` Woodhouse, David
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