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Thu, 30 Apr 2026 15:42:09 -0700 (PDT) Received: from redhat.com ([2600:382:7701:f83c:fba1:9a93:4c64:db25]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-8b53ce7e796sm4571016d6.41.2026.04.30.15.42.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2026 15:42:08 -0700 (PDT) Date: Thu, 30 Apr 2026 18:42:06 -0400 From: Brian Masney To: Conor Dooley Cc: linux-clk@vger.kernel.org, Conor Dooley , Daire McNamara , Michael Turquette , Stephen Boyd , Claudiu Beznea , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v1] clk: microchip: mpfs-ccc: fix peripheral driver registration failures after oob fix Message-ID: References: <20260430-unmade-overpay-28d175fd09a3@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260430-unmade-overpay-28d175fd09a3@spud> User-Agent: Mutt/2.3.1 (2026-03-20) On Thu, Apr 30, 2026 at 07:30:28PM +0100, Conor Dooley wrote: > From: Conor Dooley > > Commit 2f7ae8ab6aa73 ("clk: microchip: mpfs-ccc: fix out of bounds > access during output registration") fixed the out of bounds access, but > it did so by packing sparse indices into a linear space. When > peripheral drivers request clocks, they obviously don't care for this > compression and use the sparse indices, and therefore try to request the > wrong clocks or clocks that don't exist. > > The most straightforward fix here seems to stop being clever with the > packing and just overallocate the array. > > Fixes: 2f7ae8ab6aa73 ("clk: microchip: mpfs-ccc: fix out of bounds access during output registration") > Fixes: d39fb172760e ("clk: microchip: add PolarFire SoC fabric clock support") > Signed-off-by: Conor Dooley > --- > CC: Daire McNamara > CC: Michael Turquette > CC: Stephen Boyd > CC: Brian Masney > CC: Claudiu Beznea > CC: linux-riscv@lists.infradead.org > CC: linux-clk@vger.kernel.org > CC: linux-kernel@vger.kernel.org > --- > drivers/clk/microchip/clk-mpfs-ccc.c | 15 ++++----------- > 1 file changed, 4 insertions(+), 11 deletions(-) > > diff --git a/drivers/clk/microchip/clk-mpfs-ccc.c b/drivers/clk/microchip/clk-mpfs-ccc.c > index 0a76a1aaa50f7..40c17593e5941 100644 > --- a/drivers/clk/microchip/clk-mpfs-ccc.c > +++ b/drivers/clk/microchip/clk-mpfs-ccc.c > @@ -32,6 +32,7 @@ > #define MPFS_CCC_FIXED_DIV 4 > #define MPFS_CCC_OUTPUTS_PER_PLL 4 > #define MPFS_CCC_REFS_PER_PLL 2 > +#define MPFS_CCC_NUM_CLKS 16 > > struct mpfs_ccc_data { > void __iomem **pll_base; > @@ -178,7 +179,7 @@ static int mpfs_ccc_register_outputs(struct device *dev, struct mpfs_ccc_out_hw_ > return dev_err_probe(dev, ret, "failed to register clock id: %d\n", > out_hw->id); > > - data->hw_data.hws[out_hw->id - 2] = &out_hw->divider.hw; > + data->hw_data.hws[out_hw->id] = &out_hw->divider.hw; > } > > return 0; > @@ -231,17 +232,9 @@ static int mpfs_ccc_probe(struct platform_device *pdev) > { > struct mpfs_ccc_data *clk_data; > void __iomem *pll_base[ARRAY_SIZE(mpfs_ccc_pll_clks)]; > - unsigned int num_clks; > int ret; > > - /* > - * If DLLs get added here, mpfs_ccc_register_outputs() currently packs > - * sparse clock IDs in the hws array > - */ > - num_clks = ARRAY_SIZE(mpfs_ccc_pll_clks) + ARRAY_SIZE(mpfs_ccc_pll0out_clks) + > - ARRAY_SIZE(mpfs_ccc_pll1out_clks); > - > - clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_data, hw_data.hws, num_clks), > + clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_data, hw_data.hws, MPFS_CCC_NUM_CLKS), > GFP_KERNEL); > if (!clk_data) > return -ENOMEM; > @@ -255,7 +248,7 @@ static int mpfs_ccc_probe(struct platform_device *pdev) > return PTR_ERR(pll_base[1]); > > clk_data->pll_base = pll_base; > - clk_data->hw_data.num = num_clks; > + clk_data->hw_data.num = MPFS_CCC_NUM_CLKS; > clk_data->dev = &pdev->dev; > > ret = mpfs_ccc_register_plls(clk_data->dev, mpfs_ccc_pll_clks, Reviewed-by: Brian Masney I confirmed that there are 16 clock IDs defined at the bottom of include/dt-bindings/clock/microchip,mpfs-clock.h. Brian