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micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="=-5rs8WIjgleGIDKVjfbSU" Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: axis.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: GV2PR02MB8434.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 048030f8-b6af-46ff-96ae-08df20910df4 X-MS-Exchange-CrossTenant-originalarrivaltime: 02 Oct 2026 14:25:48.6363 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 78703d3c-b907-432f-b066-88f7af9ca3af X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: mX9MCEpOqnP/YNgsodpCiJEk5Nf+1kKlHP2xEGy+aV6BwtnGsWO8GDEi7CCwxxei X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR02MB6633 --=-5rs8WIjgleGIDKVjfbSU Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Andy, On Fri, 2026-10-02 at 16:12 +0300, Andy Shevchenko wrote: > On Fri, Oct 02, 2026 at 01:54:29PM +0200, Kanak Shilledar wrote: > > The device supports indirect register access to different banks. A > > specific routine needs to be followed when accessing the registers > > in > > another bank as documented in the datasheet (section 13). This is > > required for accessing registers configured via the user and > > implementing buffer support. The implementation is inspired from > > the > > icm45600 driver. The banks are defined based on their initial bank > > access code which are written to the BLK_SEL_* regs. However, there > > is a > > variation for MREG1 as User Bank 0 and MREG1 both share the same > > 0x00, > > so User Bank 1 has 0x00 and MREG1 has 0x01. When MREG1 register is > > accessed, then BLK_SEL_* is written with 0x00 instead of 0x01. All > > the > > register access goes through the 16 bit virtual regmap layered on > > top of > > the 8bit bus regmap. Bank id in the upper byte and the register > > address > > in the lower byte. Bank 0 accesses are forwarded to the bus regmap > > with > > the bank field stripped, while MREG accesses are forwarded to bank > > switching sequence. >=20 > ... >=20 > > + unsigned int val; > > + int ret, ret2; > > + > > + *idle_set =3D false; > > + > > + ret =3D regmap_read(map, INV_ICM42607_REG_MCLK_RDY, &val); > > + if (ret) > > + return ret; > > + > > + if (val & INV_ICM42607_MCLK_RDY_BIT) > > + return 0; >=20 > Why not regmap_test_bits()? I will fix it. > > + /* > > + * Clock isn't running: we're either in Sleep mode or in > > Accel LP mode > > + * running on WUOSC. Force the RC oscillator on via IDLE > > and wait for > > + * MCLK_RDY. Datasheet gives 10us (accel startup) to 200us > > (accel > > + * transition from OFF) for this to complete. > > + */ > > + ret =3D regmap_set_bits(map, INV_ICM42607_REG_PWR_MGMT0, > > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 INV_ICM42607_PWR_MGMT0_IDLE); > > + if (ret) > > + return ret; > > + > > + *idle_set =3D true; > > + > > + ret =3D regmap_read_poll_timeout(map, > > INV_ICM42607_REG_MCLK_RDY, val, > > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 val & > > INV_ICM42607_MCLK_RDY_BIT, 10, 200); > > + if (ret) { > > + ret2 =3D regmap_clear_bits(map, > > INV_ICM42607_REG_PWR_MGMT0, > > + =09 > > INV_ICM42607_PWR_MGMT0_IDLE); > > + if (ret2) > > + dev_err(regmap_get_device(map), > > + "failed to clear IDLE > > after MCLK timeout: %d\n", ret2); >=20 > Broken indentation. > Is it really important message? It is useful for indicating failure in MCLK, but I will lower the priority to either _info or _debug and fix the indentation. > > + else > > + *idle_set =3D false; > > =C2=A0 } >=20 > ... >=20 > > +static void inv_icm42607_mclk_put(struct regmap *map, bool > > idle_set) > > =C2=A0{ > > + if (idle_set) > > + regmap_clear_bits(map, INV_ICM42607_REG_PWR_MGMT0, > > + =C2=A0 INV_ICM42607_PWR_MGMT0_IDLE); > > +} >=20 > What about >=20 > if (!idle_set) > return; >=20 > regmap_clear_bits(map, INV_ICM42607_REG_PWR_MGMT0, > INV_ICM42607_PWR_MGMT0_IDLE); >=20 > ? Will incorporate the suggestion. > ... >=20 > > +static int inv_icm42607_mreg_read(struct regmap *map, unsigned int > > reg, > > + =C2=A0 u8 *data, size_t count) > > +{ > > + unsigned int val; > > + bool idle_set; > > + u8 blk_sel; > > + int ret; > > + > > + /* MREG access is one byte per transaction, no burst > > support. */ > > + if (count !=3D 1) > > + return -EINVAL; > > + > > + ret =3D inv_icm42607_blk_sel(reg, &blk_sel); > > + if (ret) > > + return ret; > > + > > + ret =3D inv_icm42607_mclk_get(map, &idle_set); > > + if (ret) > > + return ret; >=20 > > + ret =3D regmap_write(map, INV_ICM42607_REG_BLK_SEL_R, > > blk_sel); > > + if (ret) > > + goto out; >=20 > So, can we use regmap ranges instead? We can't use regmap ranges because the register accesses for different banks guarded by a specific routine of writing the bank selector, the address pointer and then finally accessing the value along with checking for timings and clocks. There is also a limitation that, accessing the registers in banks other than USER BANK 0 can only be done serially. It doesn't support bulk reads. This is documented in section 13 of the datasheet [1]. > > + ret =3D regmap_write(map, INV_ICM42607_REG_MADDR_R, > > + =C2=A0=C2=A0 FIELD_GET(INV_ICM42607_REG_ADDR_MASK, > > reg)); > > + if (ret) > > + goto out; > > + > > + fsleep(INV_ICM42607_MREG_ACCESS_DELAY_US); > > + > > + ret =3D regmap_read(map, INV_ICM42607_REG_M_R, &val); > > + if (ret) > > + goto out; > > + > > + fsleep(INV_ICM42607_MREG_ACCESS_DELAY_US); > > + > > + *data =3D val; > > +out: > > + /* Restore direct access. */ > > + ret =3D regmap_write(map, INV_ICM42607_REG_BLK_SEL_R, 0); > > + inv_icm42607_mclk_put(map, idle_set); > > + > > + return ret; > > =C2=A0} >=20 > ... >=20 > > +static const struct regmap_config inv_icm42607_regmap_config =3D { > > + .reg_bits =3D 8, > > + .val_bits =3D 8, >=20 > No cache? Why? As the virtual regmap config has some caching for USER BANK 0 registers only. The indirect banks doesn't support caching [1]. > > +}; >=20 > ... >=20 > > +static const struct regmap_config inv_icm42607_regmap_config =3D { > > + .reg_bits =3D 8, > > + .val_bits =3D 8, > > +}; >=20 > Ditto. And why they can't be deduplicated? I will remove the duplication of these regmap_configs. Thanks and Regards, Kanak Shilledar [1] Datasheet: https://www.lcsc.com/product-detail/C5129967.html --=-5rs8WIjgleGIDKVjfbSU Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQTOMrdbv2P+LZwbQtLEY9j7t8KaZwUCar++6wAKCRDEY9j7t8Ka Z5K6AQCWuRH3ximHlV4phQARVedlNj7QQ6RsSZogI1HAWV8qPQEA6lbi1w9OmI/r E8Ro1Kc8JUzo8HRT5R/dZ54vdAZEAg4= =iIXP -----END PGP SIGNATURE----- --=-5rs8WIjgleGIDKVjfbSU--