From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A305948C40B for ; Tue, 5 May 2026 17:05:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778000735; cv=none; b=UMK7Q/5Fdzmnee4u88p6qfGSR1dLeY9cEc0udCn0POXRqk5Oc2K7oaOkziEX8YRE0TbC2AQk9M3aDspjkLgupW1EfHXZ/niyK8JXs021ZvU8wqFtrZmeUy+a8FocemvAivQQAEXAjMXT+/DncNfAM3OOISvhw2TKOnhaZY2UesI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778000735; c=relaxed/simple; bh=KE6ttzAAl3wam+wCaSl3nO2l6iLsmJ6m4JvdVpqPHr4=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=RL6YEpvSRgK8HEJB5z5BGwXg+1XGGlsI8ssOfa4whb2wcBrY93k1cruk5sxJkADFNhieOB/mXwcZ9iG9VZPxIRKX23BU2hBNzcyEvHSi41z1LkS1+M9svdm4xgqhhzaVp5jcvtl0ZB5AOD4x64t63+H4hgHVU3TQV0R8ccpj7Ck= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=fpdKuWxA; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="fpdKuWxA" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9B36616A3; Tue, 5 May 2026 10:05:27 -0700 (PDT) Received: from J2N7QTR9R3.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C46333F836; Tue, 5 May 2026 10:05:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1778000733; bh=KE6ttzAAl3wam+wCaSl3nO2l6iLsmJ6m4JvdVpqPHr4=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=fpdKuWxAheJLgHm3uMupfPJH0EzcY0RRnOLTCW+y/BsMrd11EcmXgC/K+I/4VqJTI G6w1sj5tgm3GNF+v6yuKsVYVWoXOMuRAzsL6g5ZdI0qfDj+iclAGbb6aWccMBvh0jN 8XCPnw3jC2heW78r1bht+xmkrlG3iz3hhDDQzcDg= Date: Tue, 5 May 2026 18:05:25 +0100 From: Mark Rutland To: Breno Leitao Cc: Oleg Nesterov , Catalin Marinas , Will Deacon , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel-team@meta.com Subject: Re: [PATCH] arm64/fpsimd: ptrace: zero target's fpsimd_state, not the tracer's Message-ID: References: <20260505-fix_ptrace-v1-1-36ac1f6d0bfb@debian.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260505-fix_ptrace-v1-1-36ac1f6d0bfb@debian.org> Hi Breno, On Tue, May 05, 2026 at 09:02:13AM -0700, Breno Leitao wrote: > sve_set_common() is the backend for PTRACE_SETREGSET(NT_ARM_SVE) and > PTRACE_SETREGSET(NT_ARM_SSVE). Every write in the function operates on > the tracee (target) - except a single memset that uses current instead, > zeroing the tracer's saved V0-V31 / FPSR / FPCR shadow on every ptrace > SETREGSET call. Sorry about this; this was my bad and definitely needs to be fixed. > The memset is meant to give the tracee a defined zero register image > before the user-supplied payload is copied in (for partial writes, > header-only writes, and FPSIMD<->SVE format switches). Aiming it at > current both denies the tracee that clean slate and silently corrupts > the tracer. > > Due to FPSIMD lazy save/restore the wipe only takes effect when the > tracer's CPU FPSIMD binding is dropped after the memset; the next > return to userspace then reloads V0-V31, FPSR and FPCR as zero. No > signal is raised and ptrace() returns success. You're right that the corruption of the tracer's state is often masked, but I don't think the last paragraph describes the circumstances entirely accurately (e.g. if the binding is lost *before* the memset(), the issue can still occur). I think it would be better to say: The corruption of the tracer's saved FPSIMD state is not always observable. Where the tracer's state is live on a CPU, this may reused without loading the corrupted state from memory, and will eventually be written back over the corrupted state. Where the tracer's state is saved in SVE_PT_REGS_SVE format, only the FPSR and FPCR are clobbered, and the effective copy of the vectors is in the task's sve_state. > Reproducible on an arm64 kernel with SVE: a single-threaded tracer that > loads a known pattern into V0-V31, issues PTRACE_SETREGSET(NT_ARM_SVE) > on a child, and reads V0-V31 back observes them all zeroed within tens > of thousands of iterations when a sibling thread keeps stealing the > FPSIMD CPU binding. > > Fixes: 316283f276eb ("arm64/fpsimd: ptrace: Consistently handle partial writes to NT_ARM_(S)SVE") > Signed-off-by: Breno Leitao This will need to be Cc'd to stable. With the fixups above (which I assume Catalin or Will can handle): Acked-by: Mark Rutland Mark. > --- > arch/arm64/kernel/ptrace.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c > index ba5eab23fd900..4d08598e2891d 100644 > --- a/arch/arm64/kernel/ptrace.c > +++ b/arch/arm64/kernel/ptrace.c > @@ -983,8 +983,8 @@ static int sve_set_common(struct task_struct *target, > } > > /* Always zero V regs, FPSR, and FPCR */ > - memset(¤t->thread.uw.fpsimd_state, 0, > - sizeof(current->thread.uw.fpsimd_state)); > + memset(&target->thread.uw.fpsimd_state, 0, > + sizeof(target->thread.uw.fpsimd_state)); > > /* Registers: FPSIMD-only case */ > > > --- > base-commit: 9d0d467c3572e93c5faa2e5906a8bbcd70b24efd > change-id: 20260505-fix_ptrace-1bcad595c09e > > Best regards, > -- > Breno Leitao >