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Wed, 20 May 2026 16:45:37 +0000 (UTC) X-Farcaster-Flow-ID: c4cbe365-4159-4256-8585-8622e4278cdf Received: from EX19D001UWA001.ant.amazon.com (10.13.138.214) by EX19MTAUWB002.ant.amazon.com (10.250.64.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA) id 15.2.2562.37; Wed, 20 May 2026 16:45:35 +0000 Received: from 80a9970eed1e (10.187.170.17) by EX19D001UWA001.ant.amazon.com (10.13.138.214) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA) id 15.2.2562.37; Wed, 20 May 2026 16:45:34 +0000 Date: Wed, 20 May 2026 09:45:32 -0700 From: Justinien Bouron To: Leo Yan CC: Catalin Marinas , Will Deacon , David Hildenbrand , Mark Rutland , Ryan Roberts , Ada Couprie Diaz , Kevin Brodsky , "Lorenzo Stoakes" , Quentin Perret , , , Gunnar Kudrjavets Subject: Re: [PATCH] arm64: Add user and kernel page-fault tracepoints Message-ID: References: <20260520045524.75670-1-jbouron@amazon.com> <20260520073606.GA101133@e132581.arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20260520073606.GA101133@e132581.arm.com> X-Editor: VIM - Vi IMproved 9.1 X-ClientProxiedBy: EX19D043UWC003.ant.amazon.com (10.13.139.240) To EX19D001UWA001.ant.amazon.com (10.13.138.214) On Wed, May 20, 2026 at 08:36:06AM +0100, Leo Yan wrote: > On Tue, May 19, 2026 at 09:55:24PM -0700, Justinien Bouron wrote: > > [...] > > > @@ -606,6 +609,11 @@ static int __kprobes do_page_fault(unsigned long far, unsigned long esr, > > int si_code; > > int pkey = -1; > > > > + if (user_mode(regs)) > > + trace_page_fault_user(addr, regs, esr); > > + else > > + trace_page_fault_kernel(addr, regs, esr); > > Based on the discussion [1], Arm64 has already supported perf sw event > for page-faults: > > perf record -e page-faults ... > > Seems there have a plan to consolidate perf event and tracepoints but I > have no idea how it is going. This refactor/consolidation is not specific to arm64 right? I see that both x86 and riscv also have both the tracepoints and the perf event, presumably they will need to be refactored as well? > I would leave this to maintainers. Agreed. > > > + > > if (kprobe_page_fault(regs, esr)) > > return 0; > > tracepoints should be after kprobe_page_fault(), as explained [2] by Mark. Interesting. The reason I put them before the kprobe_page_fault is because this is how x86 is doing it. x86 calls kprobe_page_fault from do_kern_addr_fault / do_user_addr_fault which are called _after_ the trace_page_fault_{user,kernel}. Is there a reason why this is allowed in x86 but not arm64? Also I did not realize that there already was an attempt to add the page-fault tracepoints in the past! Best, Justinien > > Thanks, > Leo > > [1] https://lore.kernel.org/all/20250520140453.GA18711@willie-the-truck/ > [2] https://lore.kernel.org/all/aCtZfiU8bgkSAgLh@J2N7QTR9R3/