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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?TzyqBOou7+zaCZMps5JVjr8CE+ClUSAi69UQ0lYzu/ZjluTmcwnu4/tErtqz?= =?us-ascii?Q?xAYtQYd6KcVEQDSNDv9FNX22GUr0r6Cw20UAqC4C7a1nf/9MDd0N6EntGxBA?= =?us-ascii?Q?+ClesjMhe96AOTmVDJu3lcM/u+drqKfP0FLK1FUr45g63FBv3XTaklmSH4Ii?= =?us-ascii?Q?lyXoHVfuM523Ic6Hn/PRBElSHv1yooZIJNax66P9DZ/uXwqiqcVEWWzMuMGi?= =?us-ascii?Q?J5y9z3nDnqRiMUCUSXhkZYBX0sLD3Y9DpahukjGKhCP6+Dmd6UnjFrf8N4An?= =?us-ascii?Q?ZuQZGwfi4FoSafSSq8dYhMfKnFZ9NIu7eWnqwD6EIzVK74j2lghhcbOwg2NL?= =?us-ascii?Q?1i+Zext79XHmjO74JUDxKuNGBJtlAolXxuepXTN04yNfpefx0C6mL9TWXZrq?= =?us-ascii?Q?ix5QEPaGoKKb9ymzuLKUz/Ltmf0b/7nSLbSNpDr5PzxWILC3aBk873sPT/nr?= =?us-ascii?Q?4SOpBdgT68iKso6Ou1bA79P430L8NRJOfJrBglbf8pJE3G7GP7H479VFshWM?= =?us-ascii?Q?4GWKqv8E1xGdbiAPTqx26c/aut89i6MKjeIM/ajfVWtdE5gJDNkKy2Lwj047?= =?us-ascii?Q?7rZscA0VPJoReu7YgPDUKrxvqF4mz+a1vUF8/1qf7Rdm9ATzYPYUDX4IrHrS?= =?us-ascii?Q?A7G8Hr+UnZGE2+lCGXLI4GWeAkr8FkoKhK7r5Gm22fiW1KEPDctg4aK8C9OP?= =?us-ascii?Q?UOhsaH7vng4nd7HtdTe6NQDix0k1TtreWiCWzWKA7s3++bt0BLZbilYGQJsM?= =?us-ascii?Q?eVFA8H0KkGCEwWHUDMN2qnI5jHYcb25t2LLEg01enWjka5fFiCqVyjuUoVQz?= =?us-ascii?Q?K1KlgDiExZfbpgWMZ4gwZxT0ByFZ53TZOXlx0rDbs92TdNp+/lowW6ctzOTU?= =?us-ascii?Q?gjKGUTkigzpmLLVy5ozPUfC+tNPC6x0/xpdpSdkuYOt6WaB204aGV8Xnth1v?= =?us-ascii?Q?a3wacs+nEwjDGQavcGr8nh8L1h9pw+2ewY3G8bMp7W1ptfNzXqcoNM5DRMMI?= =?us-ascii?Q?jOCZMM8yydTLOkVcBR7wdu2xTyGu5k/NfxMuO8UN2Sx/BVQJRDAOY9UUKvc0?= =?us-ascii?Q?wk5dOpE3cCvrP9w7wchX2IylfYgOz1FZt8qfglP8qNOGy5OxY895jTJfDwPU?= =?us-ascii?Q?dZ1WRP+gkvWng8ZgTNSGkIcKpX7rAE+YcVawDWI8LU6+r2QzQgEh8DbWgNz9?= =?us-ascii?Q?Sbue49rBVfTvbW9Y5WOr+hbzHLWrkRk5zH2BOcqDfG3Z95/lg6BuoKjeMvtv?= =?us-ascii?Q?V2D9SnyJUjd7E7SWwIJk1UarLaq5xEigQiTvQpvqy46bWdP5Out+4zGNnJg+?= =?us-ascii?Q?/WI5ghRn1IaQ2u4jBqdiYGuhU2fGoLt2FZG2de/dZcYX7qOb83mWnLJgfiJZ?= =?us-ascii?Q?ANGoXuE/BIxYHmuYMIZjDfafBG0RisP0aXpGpTQKZhRxVy6r6NSE+k+y+u74?= =?us-ascii?Q?5UV3WQcEe0GnK/wnZZDheBIRRxfnGODJuqU6vC7x1gxWUgsuu2Y58UN4TlV4?= =?us-ascii?Q?puY8mQhpM7DFTUmjSFFgQNhxAhW2D2NT4GAtnrVfcUtI5nF/Wg7Zk/bd2O5x?= =?us-ascii?Q?zzxqNMyDLiG9wCb5aYJuTTFG75vVweKhwCEa0Mue4k/Y1vCosNnNTv3R+6wo?= =?us-ascii?Q?gAKey5yYQjaMwpFa6xMF4a//QrVRW6AAx3pVCsabBTZVmuYdtcMtMmc4mO0e?= =?us-ascii?Q?6DiKUH2eABkV9seuH6ylf0WbpmajNFGKHQuIedWd+izicdGt?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 15d4b9aa-6e73-4fd2-3969-08deb048229d X-MS-Exchange-CrossTenant-AuthSource: PA4PR04MB9366.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 May 2026 17:01:39.9570 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: JMsWTNOcFsZwi/UPpX4Qu08Ru/y0J8dW+6tsIH+ESQEaINwPhgM/WEtY++qPMDoBcB1LJCh8bWva+aFDZz5g8w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBAPR04MB7207 On Mon, May 04, 2026 at 02:33:46PM +0300, Adrian Hunter wrote: > DMA rings can be aborted either per-ring via RING_CONTROL or globally > via HC_CONTROL_ABORT. The driver currently relies on the per-ring > mechanism. > > Some Intel I3C HCI controllers require HC_CONTROL_ABORT to be asserted > before a DMA ring abort is effective. This behavior is non-standard. > Introduce a controller quirk to select the required abort method and > enable it for Intel LPSS I3C controllers. > > Signed-off-by: Adrian Hunter > --- > > > Changes in V2 and V3: > > None > > > drivers/i3c/master/mipi-i3c-hci/core.c | 18 +++++++++++++++-- > drivers/i3c/master/mipi-i3c-hci/dma.c | 27 +++++++++++++++++++++++--- > drivers/i3c/master/mipi-i3c-hci/hci.h | 2 ++ > 3 files changed, 42 insertions(+), 5 deletions(-) > > diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c > index 770235ad6b25..8274c84b16be 100644 > --- a/drivers/i3c/master/mipi-i3c-hci/core.c > +++ b/drivers/i3c/master/mipi-i3c-hci/core.c > @@ -231,7 +231,20 @@ static void i3c_hci_bus_cleanup(struct i3c_master_controller *m) > > void mipi_i3c_hci_resume(struct i3c_hci *hci) > { > - reg_set(HC_CONTROL, HC_CONTROL_RESUME); > + u32 reg = reg_read(HC_CONTROL); > + > + reg |= HC_CONTROL_RESUME; > + reg &= ~HC_CONTROL_ABORT; > + reg_write(HC_CONTROL, reg); > +} > + > +void mipi_i3c_hci_abort(struct i3c_hci *hci) > +{ > + u32 reg = reg_read(HC_CONTROL); > + > + reg &= ~HC_CONTROL_RESUME; /* Do not set resume */ > + reg |= HC_CONTROL_ABORT; > + reg_write(HC_CONTROL, reg); > } > > /* located here rather than pio.c because needed bits are in core reg space */ > @@ -1053,7 +1066,8 @@ static const struct platform_device_id i3c_hci_driver_ids[] = { > { .name = "intel-lpss-i3c", HCI_QUIRK_RPM_ALLOWED | > HCI_QUIRK_RPM_IBI_ALLOWED | > HCI_QUIRK_RPM_PARENT_MANAGED | > - HCI_QUIRK_DMA_ABORT_REQUIRES_PIO_RESET }, > + HCI_QUIRK_DMA_ABORT_REQUIRES_PIO_RESET | > + HCI_QUIRK_DMA_REQUIRES_HC_ABORT }, > { /* sentinel */ } > }; > MODULE_DEVICE_TABLE(platform, i3c_hci_driver_ids); > diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mipi-i3c-hci/dma.c > index 699c6d523eed..41bbd912df7f 100644 > --- a/drivers/i3c/master/mipi-i3c-hci/dma.c > +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c > @@ -597,6 +597,29 @@ static void hci_dma_xfer_done(struct i3c_hci *hci, struct hci_rh_data *rh) > rh_reg_write(RING_OPERATION1, op1_val); > } > > +static bool hci_dma_requires_hc_abort_quirk(struct i3c_hci *hci, struct hci_rh_data *rh) > +{ > + if (!(hci->quirks & HCI_QUIRK_DMA_REQUIRES_HC_ABORT)) > + return false; > + > + reinit_completion(&rh->op_done); > + mipi_i3c_hci_abort(hci); > + wait_for_completion_timeout(&rh->op_done, HZ); > + rh_reg_write(RING_CONTROL, rh_reg_read(RING_CONTROL) | RING_CTRL_ABORT); > + > + return true; > +} > + > +static void hci_dma_abort(struct i3c_hci *hci, struct hci_rh_data *rh) > +{ > + if (hci_dma_requires_hc_abort_quirk(hci, rh)) > + return; Move check logic here to make overall logic simple if (hci->quirks & HCI_QUIRK_DMA_REQUIRES_HC_ABORT) { hci_dma_requires_hc_abort_quirk() return; } > + > + reinit_completion(&rh->op_done); > + rh_reg_write(RING_CONTROL, rh_reg_read(RING_CONTROL) | RING_CTRL_ABORT); > + wait_for_completion_timeout(&rh->op_done, HZ); move these codes reorg into new patch. Frank > +} > + > static void hci_dma_abort_requires_pio_reset_quirk(struct i3c_hci *hci, struct hci_rh_data *rh) > { > if ((hci->quirks & HCI_QUIRK_DMA_ABORT_REQUIRES_PIO_RESET) && > @@ -630,9 +653,7 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, > hci->enqueue_blocked = true; > spin_unlock_irq(&hci->lock); > /* stop the ring */ > - reinit_completion(&rh->op_done); > - rh_reg_write(RING_CONTROL, rh_reg_read(RING_CONTROL) | RING_CTRL_ABORT); > - wait_for_completion_timeout(&rh->op_done, HZ); > + hci_dma_abort(hci, rh); > spin_lock_irq(&hci->lock); > ring_status = rh_reg_read(RING_STATUS); > if (ring_status & RING_STATUS_RUNNING) { > diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mipi-i3c-hci/hci.h > index 01237b12d32e..97c31a315a6e 100644 > --- a/drivers/i3c/master/mipi-i3c-hci/hci.h > +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h > @@ -157,9 +157,11 @@ struct i3c_hci_dev_data { > #define HCI_QUIRK_RPM_IBI_ALLOWED BIT(6) /* IBI and Hot-Join allowed while runtime suspended */ > #define HCI_QUIRK_RPM_PARENT_MANAGED BIT(7) /* Runtime PM managed by parent device */ > #define HCI_QUIRK_DMA_ABORT_REQUIRES_PIO_RESET BIT(8) /* Do PIO queue SW resets after DMA abort */ > +#define HCI_QUIRK_DMA_REQUIRES_HC_ABORT BIT(9) /* Use HC_CONTROL ABORT to abort DMA */ > > /* global functions */ > void mipi_i3c_hci_resume(struct i3c_hci *hci); > +void mipi_i3c_hci_abort(struct i3c_hci *hci); > void mipi_i3c_hci_pio_reset(struct i3c_hci *hci); > void mipi_i3c_hci_pio_reset_all_queues(struct i3c_hci *hci); > void mipi_i3c_hci_dct_index_reset(struct i3c_hci *hci); > -- > 2.51.0 >