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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-134cc2351d9sm4393185c88.9.2026.05.14.06.09.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 May 2026 06:09:36 -0700 (PDT) Date: Thu, 14 May 2026 06:09:34 -0700 From: Mike Tipton To: Abel Vesa Cc: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Odelu Kukatla , Dmitry Baryshkov , Konrad Dybcio , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/2] interconnect: qcom: eliza: Add SDCC1 slave node Message-ID: References: <20260512-eliza-interconnect-add-missing-sdcc1-slave-node-v1-0-b1edf81bac3b@oss.qualcomm.com> <20260512-eliza-interconnect-add-missing-sdcc1-slave-node-v1-2-b1edf81bac3b@oss.qualcomm.com> <0aa79750-ac75-4111-ac82-ad5672157c90@kernel.org> <3y7hyzwy7n5yqlmyywyuls374j55i7aqfgyiuabf4tubu7slut@pnhrvqulz7dh> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <3y7hyzwy7n5yqlmyywyuls374j55i7aqfgyiuabf4tubu7slut@pnhrvqulz7dh> X-Proofpoint-GUID: 9LkSaO-K8TgjR_TBFFT7hTb_Oe7Q5p60 X-Authority-Analysis: v=2.4 cv=KZbidwYD c=1 sm=1 tr=0 ts=6a05c992 cx=c_pps a=kVLUcbK0zfr7ocalXnG1qA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=kj9zAlcOel0A:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=zvVpzuEAzJinQkndZGQA:9 a=CjuIK1q_8ugA:10 a=vr4QvYf-bLy2KjpDp97w:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE0MDEzMSBTYWx0ZWRfXybPLUEr23cYm Ys9f/LctRJIio6hWpAmn2wDMb88flvI9tB8TakK9xxFNLlz09QwbCVr6w3nxNERNhZOBYsn34D0 0ermKvyyHok+N9cV8fF7dijzdZJbiDvTwmJDxQFU+maEaO2jPsphmWdnGctMQxahtdElg64Czq2 KFHPaI/wY7lrtPkiD2QL0ViTNHfKvKu+r908iIwATPD1bUcPdopq3EvVdL/Dg7RMh5EAqYJk28u 9GPG7HUrifvbK8weFPmLLuOyBfA3s69u0hRQKdIafE4BWWGtJKxWJa4DldqrE463FAQW2n6lgSy sMm+NsW6t9+77XM0djCoJ8PY296zYXVv6+pmrdNwKHrIBNnf4LO1yJQUR5P2cnwHaEeP/OVTKUW CVdU3W2XpReH1bW5oq4Gh5IgQAnwPuo3BDL3ZynlWSzWjYK2U7YbH15xFo/5v4G9aXVwzieSZ8J Vfr0+hEkfYlYJBDNZoA== X-Proofpoint-ORIG-GUID: 9LkSaO-K8TgjR_TBFFT7hTb_Oe7Q5p60 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-14_03,2026-05-13_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 bulkscore=0 impostorscore=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 malwarescore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605050000 definitions=main-2605140131 On Thu, May 14, 2026 at 01:39:24PM +0300, Abel Vesa wrote: > On 26-05-14 12:52:21, Georgi Djakov wrote: > > On 5/12/26 3:18 PM, Abel Vesa wrote: > > > The Eliza interconnect provider is missing the SDCC1 CNOC CFG slave > > > node. Add qhs_sdc1 to the provider node table and qsm_cfg links so > > > SDCC1 interconnect paths can resolve to a provider node. > > > > > > Bump the qsm_cfg link count to match the new entry. > > > > > > Fixes: a39efc80ff50 ("interconnect: qcom: Add Eliza interconnect provider driver") > > > Signed-off-by: Abel Vesa > > > --- > > > drivers/interconnect/qcom/eliza.c | 11 +++++++++-- > > > 1 file changed, 9 insertions(+), 2 deletions(-) > > > > > > diff --git a/drivers/interconnect/qcom/eliza.c b/drivers/interconnect/qcom/eliza.c > > > index a4f7903f0524..6d12a1c3c034 100644 > > > --- a/drivers/interconnect/qcom/eliza.c > > > +++ b/drivers/interconnect/qcom/eliza.c > > > @@ -127,6 +127,12 @@ static struct qcom_icc_node qhs_qup2 = { > > > .buswidth = 4, > > > }; > > > +static struct qcom_icc_node qhs_sdc1 = { > > > + .name = "qhs_sdc1", > > > + .channels = 1, > > > + .buswidth = 4, > > > +}; > > > + > > > static struct qcom_icc_node qhs_sdc2 = { > > > .name = "qhs_sdc2", > > > .channels = 1, > > > @@ -383,7 +389,7 @@ static struct qcom_icc_node qsm_cfg = { > > > .name = "qsm_cfg", > > > .channels = 1, > > > .buswidth = 4, > > > - .num_links = 29, > > > + .num_links = 30, > > > .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1, > > > &qhs_camera_cfg, &qhs_clk_ctl, > > > &qhs_crypto0_cfg, &qhs_display_cfg, > > > @@ -392,7 +398,7 @@ static struct qcom_icc_node qsm_cfg = { > > > &qhs_mss_cfg, &qhs_pcie_0_cfg, > > > &qhs_prng, &qhs_qdss_cfg, > > > &qhs_qspi, &qhs_qup1, > > > - &qhs_qup2, &qhs_sdc2, > > > + &qhs_qup2, &qhs_sdc1, &qhs_sdc2, > > > &qhs_tcsr, &qhs_tlmm, > > > &qhs_ufs_mem_cfg, &qhs_usb3_0, > > > &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, > > > > Should we also add the sdc1 to some BCM? > > AFAICT, it should not. Even downstream doesn't add it. It should be on CN0. Downstream not adding it to CN0 was also an oversight. It shouldn't make much difference in this case since CN0 is an on-off BCM and other BCMs along the path to qhs_sdc1 would indirectly keep CNOC alive, but it should technically be on CN0 just like qhs_sdc2. Thanks, Mike