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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-30294500726sm12214853eec.10.2026.05.17.20.35.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 May 2026 20:35:41 -0700 (PDT) Date: Sun, 17 May 2026 20:35:38 -0700 From: Qiang Yu To: Krzysztof Kozlowski Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, krishna.chundru@oss.qualcomm.com Subject: Re: [PATCH v3 1/4] dt-bindings: clock: qcom: Add QREF regulator supplies for glymur Message-ID: References: <20260506-qref_vote_0506-v3-0-5ab71d2e6f16@oss.qualcomm.com> <20260506-qref_vote_0506-v3-1-5ab71d2e6f16@oss.qualcomm.com> <20260514-outgoing-literate-dove-2e2a73@quoll> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Proofpoint-GUID: q0itbalBZI6StX7PxFCYJml0cjNITvkn X-Proofpoint-ORIG-GUID: q0itbalBZI6StX7PxFCYJml0cjNITvkn X-Authority-Analysis: v=2.4 cv=LKJWhpW9 c=1 sm=1 tr=0 ts=6a0a890f cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=kj9zAlcOel0A:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=12i62POrZIV3eSzbxEkA:9 a=CjuIK1q_8ugA:10 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE4MDAzMCBTYWx0ZWRfXyBo0c5jRI0R8 oZlyGm6JjKeSLlRSzCSQzboswd9+x/mBSkLB09lLagpKu4a1s+Jq3UwUu5FkRjwlSerqgCXAITv 9flC/pgSgDzigWVfBjbIhWonA+UBSxrNjGQD7xP8gZyTBh9q0LLEmex8C+GY8kKmprpzdE1YV64 SFLzctqW2ne4jwbBCZ/fs9RRXcay4VgaFcCKJEvpKaFrkfp2EMa0pzTbmAn5E74PhJCBoFhIDFq 4BeGKepZsrcv59IuMjcADMOvPBQUAnfVvkRaryHam1nBGJq8RI1mgJS7K2RoMQ2K/Vvhntun7oY amqb3ZlAh25jMlsaj+c41Lp/3rHUmyGgbgg3t6TV9nsl6xsCx2mxchG9+i7ddpSy/ni+pRtgmDe uCx/kQvGFWjZ+PUikFTnqFX9zReEuYSc88LXw/5H8AjoV8abNEjWBcXlgr8CJPM9IFgQCZIOcFN 68K1Fsh8Odc3AAWek6Q== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-18_01,2026-05-15_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 spamscore=0 adultscore=0 phishscore=0 clxscore=1015 lowpriorityscore=0 suspectscore=0 malwarescore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605180030 On Sun, May 17, 2026 at 10:28:48AM +0200, Krzysztof Kozlowski wrote: > On 17/05/2026 07:58, Qiang Yu wrote: > > On Thu, May 14, 2026 at 12:35:19PM +0200, Krzysztof Kozlowski wrote: > >> On 14/05/2026 12:22, Krzysztof Kozlowski wrote: > >>> On Wed, May 06, 2026 at 01:43:51AM -0700, Qiang Yu wrote: > >>>> Add regulator supply properties for the Glymur TCSR QREF/REFGEN blocks > >>>> required by clkref clocks. > >>>> > >>>> The vdda-qreftx*, vdda-qrefrpt*, and vdda-qrefrx* supplies map to common > >>>> QREF TX/RPT/RX components, while SoC-specific topology and instance count > >>>> differ. Document them here for qcom,glymur-tcsr. > >>>> > >>>> Signed-off-by: Qiang Yu > >>>> --- > >>>> .../bindings/clock/qcom,sm8550-tcsr.yaml | 57 ++++++++++++++++++++++ > >>>> 1 file changed, 57 insertions(+) > >>>> > >>>> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml > >>>> index 1ccdf4b0f5dd..57921cb63230 100644 > >>>> --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml > >>>> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml > >>>> @@ -51,6 +51,63 @@ properties: > >>>> '#reset-cells': > >>>> const: 1 > >>>> > >>>> + vdda-refgen-0p9-supply: true > >>>> + vdda-refgen-1p2-supply: true > >>>> + vdda-qrefrx0-0p9-supply: true > >>>> + vdda-qrefrx1-0p9-supply: true > >>>> + vdda-qrefrx2-0p9-supply: true > >>>> + vdda-qrefrx4-0p9-supply: true > >>>> + vdda-qrefrx5-0p9-supply: true > >>>> + vdda-qreftx0-0p9-supply: true > >>>> + vdda-qreftx0-1p2-supply: true > >>>> + vdda-qreftx1-0p9-supply: true > >>>> + vdda-qrefrpt0-0p9-supply: true > >>>> + vdda-qrefrpt1-0p9-supply: true > >>>> + vdda-qrefrpt2-0p9-supply: true > >>>> + vdda-qrefrpt3-0p9-supply: true > >>>> + vdda-qrefrpt4-0p9-supply: true > >>> > >>> Either I do not understand your previous explanation: > >>> CXO -> TX0 -> RPT0 -> RPT1 -> RPT2 -> RX2 -> PCIe4_PHY > >>> > >>> or this is still wrong. There is no TCSR here, so this proves nothing. > >>> If TCSR is TX0, then you do not have five of them... > >>> > >>> My previous comment stay - you are not describing the actual hardware > >>> here. > >> > >> And it should not be my task BUT YOURS to verify this in hardware > >> programming guide or manual, but nevertheless I did verify and the > >> manual DOES NOT mention these supplies. For Glymur, it mentions 8 reset > >> ports and 5 clock ports. > >> > >> No supplies at all. > >> > >> Then I went to QREF and it does mention few supplies but completely > >> different, like mx, cx, px 0.88 and px1.2, so none of this matches QREF > >> either. > >> > > > > Honestly, I couldn't find QREF LDO-related information in HPG either. > > However, you can find it on IPCAT. For example, in the glymur power grid, > > these LDOs are clearly documented under the LDOs required by each PHY, > > How is that relevant here? This is not PHY here. You are adding supplies > to TCSR. Do you understand what a supply is? > I'm telling you the fact that I see from power grid table. - Qiang Yu > > Best regards, > Krzysztof