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Date: Mon, 18 May 2026 21:45:50 +0200
From: Lukas Wunner <lukas@wunner.de>
To: "Rafael J. Wysocki" <rafael@kernel.org>
Cc: Bjorn Helgaas <helgaas@kernel.org>, linux-pci@vger.kernel.org,
	Marco Nenciarini <mnencia@kcore.it>,
	Michal Winiarski <michal.winiarski@intel.com>,
	Ilpo Jarvinen <ilpo.jarvinen@linux.intel.com>,
	Eric Chanudet <echanude@redhat.com>,
	Jean Guyader <jean.guyader@gmail.com>,
	Alex Williamson <alex@shazbot.org>, Sinan Kaya <okaya@kernel.org>,
	Mario Limonciello <superm1@kernel.org>,
	Mika Westerberg <mika.westerberg@linux.intel.com>,
	linux-kernel@vger.kernel.org, Bjorn Helgaas <bhelgaas@google.com>
Subject: Re: [PATCH v2 2/2] PCI: Wait for device readiness after D3hot ->
 D0uninitialized transition
Message-ID: <agtsbplSM7ozZcHF@wunner.de>
References: <20260518191220.636213-1-bhelgaas@google.com>
 <20260518191220.636213-3-bhelgaas@google.com>
 <CAJZ5v0iU=0SHXK9RngiYCwz5XZ0mJ+L5iy-FSWhytNgJbCam0A@mail.gmail.com>
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In-Reply-To: <CAJZ5v0iU=0SHXK9RngiYCwz5XZ0mJ+L5iy-FSWhytNgJbCam0A@mail.gmail.com>

On Mon, May 18, 2026 at 09:38:12PM +0200, Rafael J. Wysocki wrote:
> On Mon, May 18, 2026 at 9:12 PM Bjorn Helgaas <helgaas@kernel.org> wrote:
> > +++ b/drivers/pci/pci.c
> > @@ -1341,10 +1352,19 @@ int pci_power_up(struct pci_dev *dev)
> >         pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, 0);
> >
> >         /* Mandatory transition delays; see PCI PM 1.2. */
> > -       if (state == PCI_D3hot)
> > +       if (state == PCI_D3hot) {
> >                 pci_dev_d3_sleep(dev);
> > -       else if (state == PCI_D2)
> > +               if (!(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) {
> 
> Hmm.  The pmcsr value here is from before the pci_write_config_word(),
> so AFAICS it should be updated after the write.

The No_Soft_Reset bit is RO (PCIe r7.0 sec 7.5.2.2), so its value should
never change when writing zero to the Power Management Control/Status
Register.

Thanks,

Lukas