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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?B+7JaFMB2GGb9uZqUC5TZzolo7HYdnuY5ryGpsKXq69vKx0Wy936kiz1x0PD?= =?us-ascii?Q?2UxPDpB5RMQwg/k76A+U1ae8vwUXYvbi9l7pPNGaLqGeTbEw56DO+hbkZToJ?= =?us-ascii?Q?dfX57Ks0uEGz0ch33UAKk+baeQ0IuQaO9b7+GKL2iqzDVcebR0Y+WruD1oyo?= =?us-ascii?Q?AsEiFEwafDh/2NFaJkQsCjafqNKlIrWv+lnapqQn7jbI9Rs0eSB9JKRutRGW?= =?us-ascii?Q?3ORITiEbnmINEHGyMjReBivZJDKiemMDrXVUL7Dm3IuwkUg4t6fqwdyq7bSv?= =?us-ascii?Q?hwOR3A2Z/XHbjlu8yMLwGORfl10BLsubRIePJiXR8dLXnqaX2VkynS3asvxz?= =?us-ascii?Q?7/6FvWbSGgKfO00eGrmF6BCOBocHjf39meVeXWVfvHDucwoTgHopJ0Zd4jm6?= =?us-ascii?Q?na20IFHp1S1mvRFcoGiVk6KlRJMx/mGVcHUkhNa7nR8ZegnHSlhT5ufRRJjg?= =?us-ascii?Q?jtecGUIj+A7eLcH5QB5fjkPHeH7Jifu9rtJIcOSeRUNGNyFqNMiTUn6Z8zuZ?= =?us-ascii?Q?/4dEpu3kLyMqePWzv0UJDQ7vXPRn7cNqoftLLey4XMd3C/lfXlQOk+g/n4ji?= =?us-ascii?Q?uJQ6ZQUQyy9j5f0zWS1n3R7mdD5X6g4jeJYV6eLGJ/2zrm7N5X19+Gukmwrc?= =?us-ascii?Q?TRiY9axf3k3O498rchxBjUYEnD9fPxGYntCPTp3vP9N3Pn56kdOiXdHh6nrq?= =?us-ascii?Q?eIi4MqzQPz1PVcvzbViyV4/2KA82/4QLD16xGoHHF8xxEb06vpmwqaNDzj8L?= =?us-ascii?Q?xaHG+hy+A6E8qSa1gCng2AVP+aRUx37XH3DQt7VyRZwaKgu5qry6pjbY2OP0?= =?us-ascii?Q?LtUj+dBrBxScBikNLWY2Kb3FbHJ3nFIJTsZrPjcD0xKNeA378yCNiv+Pr0Hp?= =?us-ascii?Q?CHvXSjU1orpEc/yYKLW+wI5Y7kars06RUGs9yoRR7FEKGl43Jw++T+c42JfI?= =?us-ascii?Q?mBfqljPvzDyvh/MTY8wcroSh4yvDpfy6alWnfOp5VsrJq2Xv8K7FLrcPyAMk?= =?us-ascii?Q?cnNpTDiI2GKCLIBcd+uurwP1oWPxcedx7pucAV2DGRK/zya5pIKKdp//lG6z?= =?us-ascii?Q?RamzokaSblVWb1ZadQtlznSNdHtqHI1P23JEq9K7REQGEp0VcxXapKTIl63i?= =?us-ascii?Q?rkKvuCfBpX8zvuBiX96bGfG7BGuLfgjKAKneDL8jX1qrwgN9rYsAxQhFKJaT?= =?us-ascii?Q?5v9OMKNT4FSezW8UrAg1mX7UHf8TREo7f6/wWO1bNc0Xh3l64jyIokubimv4?= =?us-ascii?Q?jGFl49z6YUXEf8djr5WIgfAceI2M5FHcFP9N3Xbngt+cmYEj5Z0ovB9E1yFd?= =?us-ascii?Q?WYV8cdFL/bsbXEW5+9YwA+Dj8PlrmvajI9XKsesqKtTWZuRCW2HsFQ3RkJe5?= =?us-ascii?Q?kX+XFMpykleAlw94E8hWwKzDspH7q/QDOnAHL+LIPscgEvryME2/xWHyYQqn?= =?us-ascii?Q?knlNXtTDEzXjqPy8Rz9aVG9RxABNegdC1KQq6E0WcfbVz++OAtz5ZD50bNGj?= =?us-ascii?Q?LNscqzV3ObdM2FtXj2ApMBfHFGGzcniT+NJRJPzo96BhdMxhLvwOIJvDf/RJ?= =?us-ascii?Q?54fFODVyyc6+hR5BHqHfHF3ECmn9K7559wxZ8DrEM87grSyfD9bIzDGlY5aH?= =?us-ascii?Q?lNxKPlY+cd2egeakyH79fCkAVquuaUi2J+XFXmwmVSgr5AgcgNIjxh89U0q/?= =?us-ascii?Q?CBE8AHhf8X4Medwc5Nch0AQhnShkvhfr+oovfgkklnwRD0JTz0yt6WHJPbu5?= =?us-ascii?Q?uE/rSfcOIw=3D=3D?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 69def77d-38a3-4045-41a4-08dec0520df7 X-MS-Exchange-CrossTenant-AuthSource: PA4PR04MB9366.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jun 2026 02:52:58.8632 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: rX/PuOIg0N4hthHPL5/ZQPl8nm/yObsoSg63EBL9SWAEkXWYWZquVubW+8dsBNoh806hadmMIXQlZqe1li6bog== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU4PR04MB12149 On Fri, May 15, 2026 at 07:26:13PM +0300, Adrian Hunter wrote: > Some Intel I3C HCI controllers cannot reliably restart a DMA ring after an > ABORT. Additional queue resets are required to recover, and must be > performed using PIO reset bits even while operating in DMA mode. > > This behavior is non-standard. Introduce a controller quirk to opt into > the required PIO queue resets after a DMA ring abort, and enable it for > Intel LPSS I3C controllers. > > Signed-off-by: Adrian Hunter > --- Reviewed-by: Frank Li > > > Changes in V4: > > Inline HCI_QUIRK_DMA_ABORT_REQUIRES_PIO_RESET check at call site > instead of using a helper function > > Changes in V2 and V3: > > None > > > drivers/i3c/master/mipi-i3c-hci/core.c | 15 ++++++++++++++- > drivers/i3c/master/mipi-i3c-hci/dma.c | 4 ++++ > drivers/i3c/master/mipi-i3c-hci/hci.h | 2 ++ > 3 files changed, 20 insertions(+), 1 deletion(-) > > diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c > index 44617eb3a3f1..770235ad6b25 100644 > --- a/drivers/i3c/master/mipi-i3c-hci/core.c > +++ b/drivers/i3c/master/mipi-i3c-hci/core.c > @@ -240,6 +240,18 @@ void mipi_i3c_hci_pio_reset(struct i3c_hci *hci) > reg_write(RESET_CONTROL, RX_FIFO_RST | TX_FIFO_RST | RESP_QUEUE_RST); > } > > +#define ALL_QUEUES_RST (CMD_QUEUE_RST | RESP_QUEUE_RST | RX_FIFO_RST | TX_FIFO_RST | IBI_QUEUE_RST) > + > +void mipi_i3c_hci_pio_reset_all_queues(struct i3c_hci *hci) > +{ > + u32 regval; > + > + reg_write(RESET_CONTROL, ALL_QUEUES_RST); > + if (readx_poll_timeout_atomic(reg_read, RESET_CONTROL, regval, > + !(regval & ALL_QUEUES_RST), 0, 20)) > + dev_err(&hci->master.dev, "%s: Reset queues failed\n", __func__); > +} > + > /* located here rather than dct.c because needed bits are in core reg space */ > void mipi_i3c_hci_dct_index_reset(struct i3c_hci *hci) > { > @@ -1040,7 +1052,8 @@ MODULE_DEVICE_TABLE(acpi, i3c_hci_acpi_match); > static const struct platform_device_id i3c_hci_driver_ids[] = { > { .name = "intel-lpss-i3c", HCI_QUIRK_RPM_ALLOWED | > HCI_QUIRK_RPM_IBI_ALLOWED | > - HCI_QUIRK_RPM_PARENT_MANAGED }, > + HCI_QUIRK_RPM_PARENT_MANAGED | > + HCI_QUIRK_DMA_ABORT_REQUIRES_PIO_RESET }, > { /* sentinel */ } > }; > MODULE_DEVICE_TABLE(platform, i3c_hci_driver_ids); > diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mipi-i3c-hci/dma.c > index 8e27fb6f18f5..906de7dbfdb5 100644 > --- a/drivers/i3c/master/mipi-i3c-hci/dma.c > +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c > @@ -638,6 +638,10 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, > } > } > > + if ((hci->quirks & HCI_QUIRK_DMA_ABORT_REQUIRES_PIO_RESET) && > + (rh_reg_read(RING_STATUS) & RING_STATUS_ABORTED)) > + mipi_i3c_hci_pio_reset_all_queues(hci); > + > hci_dma_xfer_done(hci, rh); > > for (i = 0; i < n; i++) { > diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mipi-i3c-hci/hci.h > index 83d4f13a68a3..01237b12d32e 100644 > --- a/drivers/i3c/master/mipi-i3c-hci/hci.h > +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h > @@ -156,10 +156,12 @@ struct i3c_hci_dev_data { > #define HCI_QUIRK_RPM_ALLOWED BIT(5) /* Runtime PM allowed */ > #define HCI_QUIRK_RPM_IBI_ALLOWED BIT(6) /* IBI and Hot-Join allowed while runtime suspended */ > #define HCI_QUIRK_RPM_PARENT_MANAGED BIT(7) /* Runtime PM managed by parent device */ > +#define HCI_QUIRK_DMA_ABORT_REQUIRES_PIO_RESET BIT(8) /* Do PIO queue SW resets after DMA abort */ > > /* global functions */ > void mipi_i3c_hci_resume(struct i3c_hci *hci); > void mipi_i3c_hci_pio_reset(struct i3c_hci *hci); > +void mipi_i3c_hci_pio_reset_all_queues(struct i3c_hci *hci); > void mipi_i3c_hci_dct_index_reset(struct i3c_hci *hci); > void amd_set_od_pp_timing(struct i3c_hci *hci); > void amd_set_resp_buf_thld(struct i3c_hci *hci); > -- > 2.51.0 >