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Mon, 25 May 2026 00:06:51 -0700 (PDT) X-Received: by 2002:a17:903:1212:b0:2bd:4d9e:ab27 with SMTP id d9443c01a7336-2beb05822d6mr148296545ad.17.1779692810948; Mon, 25 May 2026 00:06:50 -0700 (PDT) Received: from hu-arakshit-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2beb58b387dsm87575635ad.50.2026.05.25.00.06.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 May 2026 00:06:50 -0700 (PDT) Date: Mon, 25 May 2026 12:36:43 +0530 From: Abhinaba Rakshit To: Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , "James E.J. Bottomley" , "Martin K. Petersen" , Adrian Hunter , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neeraj Soni , Harshal Dev , Kuldeep Singh Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio Subject: Re: [PATCH v9 0/5] Enable ICE clock scaling Message-ID: References: <20260525-enable-ice-clock-scaling-v9-0-c84613e9ce47@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20260525-enable-ice-clock-scaling-v9-0-c84613e9ce47@oss.qualcomm.com> X-Proofpoint-ORIG-GUID: athwSIOU4zf7w7xRrYFwh66OzY0hOOdO X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTI1MDA2OSBTYWx0ZWRfX6zz6PC1ystHR llyxRXKz7owqACFxT4EZipvoywF/j+5RwnvEigcG07iZK0q9tdAhhEm6knnit5R82C8yqK//VpT 6hJOcgajezvJG/2WXhwYy9uZBh26/r/NU9Jg0a/vOhx/dq77331o37/+tID1I7rPf12OtmqxpQi 1/5ekYjahptT31W6kyygxWYBS7yrY+E1bkztHCQG3n8Oc6ZctUVK0qWYV4dAofTo9vWcOHP8UmX IQsRKssUY0u9a7xuWIfRMg9OXGNRdRwPx949paO2YtxzPAGVql2MrT/K3rorZ3Ov3RVq7dS2SCD SlA0sUSE0itEGUFG4MPcKwTilkXSoaTAxO4atgiYqxw03y9d35nt22c7rJeRLWye3bzxExzGZ+7 3rHApgP58E0t2uvxxw4wIsn9rY4Rt9qUr7vohoMymmrH7/0vqyKR2Z7NFY2HODHaDML/kTF8m41 7rA09Jdnoe2b3IUGH7Q== X-Proofpoint-GUID: athwSIOU4zf7w7xRrYFwh66OzY0hOOdO X-Authority-Analysis: v=2.4 cv=Xca5Co55 c=1 sm=1 tr=0 ts=6a13f50c cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=p6yxZNB5brmi-_xxTTcA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-25_02,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 malwarescore=0 adultscore=0 priorityscore=1501 impostorscore=0 clxscore=1015 lowpriorityscore=0 bulkscore=0 phishscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605250069 On Mon, May 25, 2026 at 12:55:47AM +0530, Abhinaba Rakshit wrote: > Introduce support for dynamic clock scaling of the ICE (Inline Crypto Engine) > using the OPP framework. During ICE device probe, the driver now attempts to > parse an optional OPP table from the ICE-specific device tree node for > DVFS-aware operations. API qcom_ice_scale_clk is exposed by ICE driver > and is invoked by UFS host controller driver in response to clock scaling > requests, ensuring coordination between ICE and host controller. > > For MMC controllers that do not support clock scaling, the ICE clock frequency > is kept aligned with the MMC controller’s clock rate (TURBO) to ensure > consistent operation. > > Dynamic clock scaling based on OPP tables enables better power-performance > trade-offs. By adjusting ICE clock frequencies according to workload and power > constraints, the system can achieve higher throughput when needed and > reduce power consumption during idle or low-load conditions. > > The OPP table remains optional, absence of the table will not cause > probe failure. However, in the absence of an OPP table, ICE clocks will > remain at their default rates, which may limit performance under > high-load scenarios or prevent performance optimizations during idle periods. > > Testing: > * dtbs_check > * Validated on Rb3Gen2 and qcs8300-ride-sx > > Merge Order and Dependencies > ============================ > > Patch 2 is dependent on patch 1 for the qcom_ice_scale_clk API to be available. > Patch 3 is dependent on patch 1 for the qcom_ice_scale_clk API to be available. > > Due to dependency, all patches should go through Qcom SoC tree. > > This patchset supersedes earlier ICE clock scaling series (v1–v8) with updated dependencies. > Hence, this patchset also *Depends-On* the following patchseries: > > [1] Add explicit clock vote and enable power-domain for QCOM-ICE > https://lore.kernel.org/all/20260416-qcom_ice_power_and_clk_vote-v5-0-5ccf5d7e2846@oss.qualcomm.com/ > > [2] Enable Inline crypto engine for kodiak and monaco > https://lore.kernel.org/all/20260310113557.348502-1-neeraj.soni@oss.qualcomm.com/ > > [3] Enable iface clock and power domain for kodiak and monaco ice sdhc > https://lore.kernel.org/linux-arm-msm/20260409-ice_emmc_clock_addition-v2-0-90bbcc057361@oss.qualcomm.com/ > > Signed-off-by: Abhinaba Rakshit > --- > Changes in v9: > - Kodiak ICE eMMC OPP-table entry corresponding to 300MHz is updated with SVS_L1. > - Add 75MHz for Monaco ICE eMMC OPP-table. > - Fix error handling and initialization of has_opp variable. > - Pass ULONG_MAX as target freq instead of INT_MAX from sdhci_ice_init as it better adjusts the data-type of > the function qcom_ice_scale_clk. > - Link to v8: https://lore.kernel.org/r/20260409-enable-ice-clock-scaling-v8-0-ca1129798606@oss.qualcomm.com Hello, It appears that some of the dependencies for this patch series have already been picked, and there have also been recent changes in the ICE driver that conflict with my patches. Please avoid picking this patch series for now. I will post a new version based on the tip of linux-next, with the ICE driver conflicts resolved. Abhinaba Rakshit