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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?dyD/jSMGZysjB+Tmzp/T3eODZUkjD6m/2/ec1Sl/4RZWkehPUkAb6jc5Rtq5?= =?us-ascii?Q?pwza2u/L2QWhrjSzK0h2pEWLsFntI1Byy3uDkS+Adlm23vct7p4gnu/GHcDw?= =?us-ascii?Q?upp29Ci5mnLCvWawVRB0vPjJrxpEfP0sZr4iFO10xXswhZE+BHancTeQDCoA?= =?us-ascii?Q?zAOTaol3JcXc30/XfeJNo1jEJdXgGB7N1lmkz7pTl9brnYtH9yUKCLSrrH1m?= =?us-ascii?Q?RSTaI1dZtMLs3m0oZUlUf/4xDcMTQ6IdVzpPatOGwDmNWN2h1xgwaLOSwMds?= =?us-ascii?Q?CegyGirGVVGn1cC+BC++Y9oZxrKmApE/pOjXd6SY5uI9oAdmjmzoAmICxxfo?= =?us-ascii?Q?KDFCt9Xmtj6EePhep8CAraJc/4hi8wNyCMlL2Kn/aQ+vt+bo2Gu3p0EZw/zk?= =?us-ascii?Q?EYmPhodE+1VeVIVGaz3AWem04ivYXgcI6COyQrFrTP0y9ld9ZR5q/GlcnCSu?= =?us-ascii?Q?AQeDpmdzhQp1wbByMyMHwgbfb9tmEhWAbFev6wIkOa+BqAKCd47vdtvs67Dm?= =?us-ascii?Q?4jUGN9Dr3m3+rcqB6Bwo7mmdx9UYFkWJHyovUUb1MYnetPKq53mDrCGRqK+T?= =?us-ascii?Q?spAUReyfKE98WlrrsFlodMfFrO2uQB9PSPWHbjVu9KshUqMxXh6SL1OQ0LPV?= =?us-ascii?Q?FDonbVIpu8MR+2+ypElmXKSLtu4r/jEAVJkITPsQ9UltbDNhdUVrM520d6Vk?= =?us-ascii?Q?8jlbukA8IKsXRBlhLZB+onzH9N9Ay6WXO00ln1DgxHwuZDeJv5l8rSdy3wmH?= =?us-ascii?Q?L+F6h0WATNbP66Vt7gpE9Sk2Ly8t/KAXQJeTWXV890EEQG2IYXR7QhX2+V4B?= =?us-ascii?Q?n1iQ3s6Pg7cMJUi1XiNxFzZKFSJrGVWUzxRCPOr9awDKbiqGwXOQehIHvNGz?= =?us-ascii?Q?q3KDJYrmmXMGIo5FsnduD+Qf+HrPRAiuG7L2u2PV0rWi2I3sm1+3QpqiYqlu?= =?us-ascii?Q?xNFTCFiZo8iyFkyt05xLVkX9RYXiAL7A+80A39RPeUSuzDOTX+m8sNQtA1PC?= =?us-ascii?Q?JuuClMpAWIHD3RuMWGmsm9poXFlFsAXjSLqH3zctauXMv+F0oCtgQTjRhaoT?= =?us-ascii?Q?yN2rRYAzq78UNvYYp89B/YILqmfnUVVlGBWs3jyKd2dm1R/HwtA54Bn/Wcrt?= =?us-ascii?Q?3AJ+nJfAYYYhkvIEVUkx+IT18K93kZDtl+dBwFuf0AGiUa/2Xiwklx13hrkH?= =?us-ascii?Q?3eIuABIMXcQdA1loj5V8F2AWmkTUqd5Gt2vixZgAzVSXpMyOoI6S6Eb+xho6?= =?us-ascii?Q?km1DrhTHuCLgC03dsaMmJFIUDxo5yLNaAJbdmYlwLlh+jZG634LqjOcO7N5H?= =?us-ascii?Q?agbv2u7CW01A13RGidU1B24gQFBHfjeXg6bF9HmYtD+YVO2wxhmVhFIt9w7b?= =?us-ascii?Q?+CNBoslglznzx7gyzGdeF0V7rVqCr+B9PO/WMXczRizU4CZmy2fBRyFTAjlE?= =?us-ascii?Q?XMxfL17p3peV8yEqLPGLW5A2k7dMSvASOU0FGp4Fd53or5V4eQBgSpIH6wyn?= =?us-ascii?Q?Q612No/DN/aU13vwCOkEwKBF6GnC7W09DCJIAiqn6m0aVV/sCkZHa0IdwkvW?= =?us-ascii?Q?UzpgTpg2iq3kYgfbnZimgIWb/97aPD3fxKM6SPuMuNkV2vp3wHdnIqtY7IRy?= =?us-ascii?Q?YdwynK4suTgFfxk3P6+NY3zY2Z2p+I+FjmLxQIMqiMM7iAMDjifmDzPpb2Il?= =?us-ascii?Q?8rDoBGme8WUH+9UcpTu1zv6G5BjLQNFx5nuucFsGhmwNX8d1u6fWs7y86Fo2?= =?us-ascii?Q?kmkXM6++yCnDWSAz2pMtUCvHZ43QKnU5uz3FIsvV/qtdFHqNU+QE?= X-OriginatorOrg: bp.renesas.com X-MS-Exchange-CrossTenant-Network-Message-Id: 031daf30-bfd7-4c73-b0cc-08debcc01041 X-MS-Exchange-CrossTenant-AuthSource: TYCPR01MB11947.jpnprd01.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 May 2026 13:50:22.9152 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 53d82571-da19-47e4-9cb4-625a166a4a2a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: bgQJ2v2CvIrUmZo07cLhaiUCmphX81aMJGhCfeJvpnbWraxqukBM5kaGS6HyHQb52BP2pLEpHQIdILALgxh4E5EeNsfk3WCx66dCTPiF1B2CpU6rQhp7GUmf0Ng6Bw7+ X-MS-Exchange-Transport-CrossTenantHeadersStamped: OSRPR01MB11420 On Tue, May 26, 2026 at 11:47:02AM +0300, Claudiu Beznea wrote: > From: Claudiu Beznea > > Subsequent patches will add suspend/resume and cyclic DMA support to the > rz-dmac driver. This support needs to work on SoCs where power to most > components (including DMA) is turned off during system suspend. For this, > some channels (for example cyclic ones) may need to be paused and resumed > manually by the DMA driver during system suspend/resume. > > Refactor the pause/resume support so the same code can be reused in the > system suspend/resume path. > Tested-by: Tommaso Merciai > Tested-by: John Madieu > Signed-off-by: Claudiu Beznea > --- > > Changes in v6: > - collected tags > > Changes in v5: > - none > > Changes in v4: > - reset channel->status in rz_dmac_free_chan_resources() and > rz_dmac_terminate_all() > > Changes in v3: > - none, this patch new new > > drivers/dma/sh/rz-dmac.c | 73 ++++++++++++++++++++++++++++++++++------ > 1 file changed, 62 insertions(+), 11 deletions(-) > > diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c > index 1f884ec101f8..557364443a5f 100644 > --- a/drivers/dma/sh/rz-dmac.c > +++ b/drivers/dma/sh/rz-dmac.c > @@ -18,6 +18,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -63,6 +64,14 @@ struct rz_dmac_desc { > > #define to_rz_dmac_desc(d) container_of(d, struct rz_dmac_desc, vd) > > +/** > + * enum rz_dmac_chan_status: RZ DMAC channel status > + * @RZ_DMAC_CHAN_STATUS_PAUSED: Channel is paused though DMA engine callbacks > + */ > +enum rz_dmac_chan_status { > + RZ_DMAC_CHAN_STATUS_PAUSED, > +}; > + > struct rz_dmac_chan { > struct virt_dma_chan vc; > void __iomem *ch_base; > @@ -74,6 +83,8 @@ struct rz_dmac_chan { > dma_addr_t src_per_address; > dma_addr_t dst_per_address; > > + unsigned long status; > + > u32 chcfg; > u32 chctrl; > int mid_rid; > @@ -491,6 +502,8 @@ static void rz_dmac_free_chan_resources(struct dma_chan *chan) > channel->mid_rid = -EINVAL; > } > > + channel->status = 0; > + > spin_unlock_irqrestore(&channel->vc.lock, flags); > > vchan_free_chan_resources(&channel->vc); > @@ -589,6 +602,9 @@ static int rz_dmac_terminate_all(struct dma_chan *chan) > } > > vchan_get_all_descriptors(&channel->vc, &head); > + > + channel->status = 0; > + > spin_unlock_irqrestore(&channel->vc.lock, flags); > vchan_dma_desc_free_list(&channel->vc, &head); > > @@ -795,35 +811,70 @@ static enum dma_status rz_dmac_tx_status(struct dma_chan *chan, > return status; > } > > -static int rz_dmac_device_pause(struct dma_chan *chan) > +static int rz_dmac_device_pause_set(struct rz_dmac_chan *channel, > + unsigned long set_bitmask) > { > - struct rz_dmac_chan *channel = to_rz_dmac_chan(chan); > + int ret = 0; > u32 val; > > - guard(spinlock_irqsave)(&channel->vc.lock); > + lockdep_assert_held(&channel->vc.lock); > > if (!rz_dmac_chan_is_enabled(channel)) > return 0; > > + if (rz_dmac_chan_is_paused(channel)) > + goto set_bit; > + > rz_dmac_ch_writel(channel, CHCTRL_SETSUS, CHCTRL, 1); > - return read_poll_timeout_atomic(rz_dmac_ch_readl, val, > - (val & CHSTAT_SUS), 1, 1024, > - false, channel, CHSTAT, 1); > + ret = read_poll_timeout_atomic(rz_dmac_ch_readl, val, > + (val & CHSTAT_SUS), 1, 1024, false, > + channel, CHSTAT, 1); > + > +set_bit: > + channel->status |= set_bitmask; > + > + return ret; > } > > -static int rz_dmac_device_resume(struct dma_chan *chan) > +static int rz_dmac_device_pause(struct dma_chan *chan) > { > struct rz_dmac_chan *channel = to_rz_dmac_chan(chan); > - u32 val; > > guard(spinlock_irqsave)(&channel->vc.lock); > > + return rz_dmac_device_pause_set(channel, BIT(RZ_DMAC_CHAN_STATUS_PAUSED)); > +} > + > +static int rz_dmac_device_resume_set(struct rz_dmac_chan *channel, > + unsigned long clear_bitmask) > +{ > + int ret = 0; > + u32 val; > + > + lockdep_assert_held(&channel->vc.lock); > + > /* Do not check CHSTAT_SUS but rely on HW capabilities. */ > > rz_dmac_ch_writel(channel, CHCTRL_CLRSUS, CHCTRL, 1); > - return read_poll_timeout_atomic(rz_dmac_ch_readl, val, > - !(val & CHSTAT_SUS), 1, 1024, > - false, channel, CHSTAT, 1); > + ret = read_poll_timeout_atomic(rz_dmac_ch_readl, val, > + !(val & CHSTAT_SUS), 1, 1024, false, > + channel, CHSTAT, 1); > + > + channel->status &= ~clear_bitmask; > + > + return ret; > +} > + > +static int rz_dmac_device_resume(struct dma_chan *chan) > +{ > + struct rz_dmac_chan *channel = to_rz_dmac_chan(chan); > + > + guard(spinlock_irqsave)(&channel->vc.lock); > + > + if (!(channel->status & BIT(RZ_DMAC_CHAN_STATUS_PAUSED))) > + return 0; > + > + return rz_dmac_device_resume_set(channel, BIT(RZ_DMAC_CHAN_STATUS_PAUSED)); > } > > /* > -- > 2.43.0 >