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Fri, 29 May 2026 16:20:19 -0700 Date: Fri, 29 May 2026 16:20:17 -0700 From: Nicolin Chen To: Suravee Suthikulpanit CC: , , , , , , , , , , , , , , , Subject: Re: [PATCH v2 25/26] iommu/amd: Handle set/get command for AMD vIOMMU Message-ID: References: <20260528051738.596013-1-suravee.suthikulpanit@amd.com> <20260528051738.596013-26-suravee.suthikulpanit@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20260528051738.596013-26-suravee.suthikulpanit@amd.com> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001E9:EE_|SJ0PR12MB7006:EE_ X-MS-Office365-Filtering-Correlation-Id: 26d66aec-ffb1-456a-7170-08debdd8e1aa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700016|1800799024|82310400026|7416014|56012099006|4143699003|11063799006|18002099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: n550gDw8jpsuQa9BoUCJBuborxXL/Nt8nKgf6kj6ec3hqPmWBbDpfrkF6yCCBfJkhGbAyLxIzyNv86zPDR4kb0qRKjAeqV0/GyqiVdrhsNrKVmRLtK+esdneCfYCnPH8JT6D8YouzFcfBf5j44FD/4m+HVFgY0UEJ0ZOAnNDtEQpP+6VH15/bSsV6UeyKa0af3r7BaFwXW0CDAyaXg61C6zl/17M5wDxlgit1ui4tN3mfvmHkBj9Xh0Rk39V4IlmwmLiqijGledVKadYOX+SV9dckNX+wZfAyArorZt0UfztqlR+SYXWi7CHsvoUQ2Yp1zBNYVte9vvzQUHRDXNtgGlK1cd+QiUw+M/UWixx97ZMIK/7zmAZPeythwz5tOq4I7bM8mEmAyJ8rkNxy5h3xvDibxJ1kylacHMvpdsgbzFixiF/6y+8YW+6MJ4wyX0u X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 May 2026 23:20:32.9660 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 26d66aec-ffb1-456a-7170-08debdd8e1aa X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001E9.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB7006 On Thu, May 28, 2026 at 05:17:37AM +0000, Suravee Suthikulpanit wrote: > Guest kernel programs guest Command Buffer, Event Log, and PPR Log > (a.k.a hardware queue) settings via guest control MMIO register > (guest MMIO offset 0x18). Accesses to the register is trapped by VMM (QEMU) > and information is passed as IOMMU_VIOMMU_OPTION to host IOMMU driver via > struct iommufd_viommu_ops set_command() and get_command(). > > Provides AMD IOMMU driver hooks to handle set/get operations for the > guest control MMIO register, which uses key parameter as AMD IOMMU MMIO > offset. The value parameter contains the value of the corresponding guest > MMIO register, which is converted to the format of AMD vIOMMU VF Control > MMIO registers then programed onto the hardware. So the whole set_command/get_command thing is to MMIO a control register? I doubt this is a right ioctl(s) as it can be abused. Looking at the details: > + switch (offset) { > + case MMIO_CONTROL_OFFSET: > + { > + /* VFCTRL offset 20h */ > + val = readq(vfctrl + 0x20); > + val &= ~(0x3ULL << 8); > + tmp = GET_CTRL_BITS(ctrl, CONTROL_CMDBUF_EN, 1); // [12] > + val |= (tmp << 8); This is to enable a hw_queue. So it could be marked when a hw_queue is allocated; IMHO, VMM should only allocate the hw_queue, when the guest really uses (enables) the buffer. > + tmp = GET_CTRL_BITS(ctrl, CONTROL_COMWAIT_EN, 1); // [4] > + val |= (tmp << 9); > + writeq(val, vfctrl + 0x20); The spec suggests to set this with CmdBufEn, so it may be a vendor (or hw_queue type) specific flag in structu iommu_hw_queue_alloc? And similar comments to the event log and pri log buffers as well. Overall, VMM should control the timings of allocating these viommu hw_queue objects; then kernel would just enable them accordingly. Nicolin