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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3081eb8f8b2sm14166142eec.27.2026.06.15.01.46.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jun 2026 01:46:03 -0700 (PDT) Date: Mon, 15 Jun 2026 01:46:02 -0700 From: Qiang Yu To: Konrad Dybcio Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, krishna.chundru@oss.qualcomm.com Subject: Re: [PATCH v4 3/7] clk: qcom: tcsrcc-glymur: Migrate tcsr_pcie_N_clkref_en to clk_ref common helper Message-ID: References: <20260527-tcsr_qref_0527-v4-0-ded83866c9d9@oss.qualcomm.com> <20260527-tcsr_qref_0527-v4-3-ded83866c9d9@oss.qualcomm.com> <747f0319-68e1-4cd7-9dd1-4a675d882f99@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <747f0319-68e1-4cd7-9dd1-4a675d882f99@oss.qualcomm.com> X-Proofpoint-GUID: U1Zcsb0869ra64WABVhQx8SWeV5SYvC8 X-Proofpoint-ORIG-GUID: U1Zcsb0869ra64WABVhQx8SWeV5SYvC8 X-Proofpoint-Spam-Info: AW1haW4tMjYwNjE1MDA5MSBTYWx0ZWRfX9gpRTOfuDdeb JrDz3EZUve/sXRzaIUunqCwLnX5i+04gX2LUz4Ppb5j0QVVRGT9BYcnNUuJkOS8MjUuuzUefuUG GLZYVx8j14BA1yZXjyz/HSCEr1onUoo= X-Authority-Analysis: v=2.4 cv=JLYLdcKb c=1 sm=1 tr=0 ts=6a2fbbcd cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=kj9zAlcOel0A:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=9x36BgKddDksvwc1ZLQA:9 a=CjuIK1q_8ugA:10 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjE1MDA5MSBTYWx0ZWRfX6LZtWAXb00CN e2mD6Zy9Xaid2JN7QM6VtAbtLIX160jFjrLJh2geekLEmeXVWTwkunzOKS18l3Loe352Hknu1Gk Ch3xawnU20QBErA91UKufBbNz4Gh/OxbD8VooIm5xepw97n6Lt6fTmARvuOIwPSG7AK/bzQU5R3 56IjCUvkf+IBPI0HuQV05628WRpwdhtg7Z+UGh17irjmKT/8ctAhZyLPRkKwJg4hekAGyrEfrD7 rFVlmDY7DDJb8Zsqvzpqsku1+0GktiPq9jraTKT4ogUfs/GUfdtRqNsGXmwY7kYqMZOoIvSUmHQ kFtTgfJvh375CgTeCNkLzP70UOXIYY63fZ2BZb+CmSozEp1J3p9NYsrskrz4HFC1veQm93upf0+ uRoMUFkvlJH9/gX8Rz6jnXIy32YBDhtC9Gnj3w/NA/7Ph6+UBg+weYzDF7ojsddXgC0JdH4S2nk hiSKwGqbmCKGIESaCkA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-15_02,2026-06-12_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 impostorscore=0 bulkscore=0 adultscore=0 malwarescore=0 phishscore=0 suspectscore=0 priorityscore=1501 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606040000 definitions=main-2606150091 On Tue, Jun 09, 2026 at 03:02:27PM +0200, Konrad Dybcio wrote: > On 5/28/26 4:29 AM, Qiang Yu wrote: > > Replace local clk_branch-based clkref definitions with descriptor-based > > registration via qcom_clk_ref_probe(). > > > > This keeps the glymur driver focused on clock metadata and reuses common > > runtime logic for regulator handling, enable/disable sequencing, and OF > > provider wiring. > > > > Signed-off-by: Qiang Yu > > --- > > You can remove the of.h include. Apart from that: > > Reviewed-by: Konrad Dybcio > > Also, attaching a diff to complete the regulator map. I'm fairly sure > these are correct, but it never hurts to triple-check. > > You can add: > > Co-developed-by: Konrad Dybcio > Signed-off-by: Konrad Dybcio > > if you squash them together. FYI e.g. the tertiary USB QMPPHY would > only start every 20 boots or so without this, running on pure luck.. > Okay, will sqash them and add above tags in next version. - Qiang Yu > Konrad > > diff --git a/drivers/clk/qcom/tcsrcc-glymur.c b/drivers/clk/qcom/tcsrcc-glymur.c > index e317003398d1..eb4ee8ec9ad7 100644 > --- a/drivers/clk/qcom/tcsrcc-glymur.c > +++ b/drivers/clk/qcom/tcsrcc-glymur.c > @@ -21,6 +21,14 @@ static const char * const glymur_tcsr_tx0_rx5_regulators[] = { > "vdda-qreftx0-1p2", > }; > > +static const char * const glymur_tcsr_tx1_rpt0_rx0_regulators[] = { > + "vdda-refgen4-0p9", > + "vdda-refgen4-1p2", > + "vdda-qreftx1-0p9", > + "vdda-qrefrpt0-0p9", > + "vdda-qrefrx0-0p9", > +}; > + > static const char * const glymur_tcsr_tx1_rpt01_rx1_regulators[] = { > "vdda-refgen4-0p9", > "vdda-refgen4-1p2", > @@ -40,6 +48,15 @@ static const char * const glymur_tcsr_tx1_rpt012_rx2_regulators[] = { > "vdda-qrefrx2-0p9", > }; > > +static const char * const glymur_tcsr_tx1_rpt34_rx4_regulators[] = { > + "vdda-refgen2-0p9", > + "vdda-refgen2-1p2", > + "vdda-qreftx1-0p9", > + "vdda-qrefrpt3-0p9", > + "vdda-qrefrpt4-0p9", > + "vdda-qrefrx4-0p9", > +}; > + > static const struct regmap_config tcsr_cc_glymur_regmap_config = { > .reg_bits = 32, > .reg_stride = 4, > @@ -52,6 +69,8 @@ static const struct qcom_clk_ref_desc tcsr_cc_glymur_clk_descs[] = { > [TCSR_EDP_CLKREF_EN] = { > .name = "tcsr_edp_clkref_en", > .offset = 0x60, > + .regulator_names = glymur_tcsr_tx1_rpt0_rx0_regulators, > + .num_regulators = ARRAY_SIZE(glymur_tcsr_tx1_rpt0_rx0_regulators), > }, > [TCSR_PCIE_1_CLKREF_EN] = { > .name = "tcsr_pcie_1_clkref_en", > @@ -80,34 +99,50 @@ static const struct qcom_clk_ref_desc tcsr_cc_glymur_clk_descs[] = { > [TCSR_USB2_1_CLKREF_EN] = { > .name = "tcsr_usb2_1_clkref_en", > .offset = 0x6c, > + .regulator_names = glymur_tcsr_tx1_rpt34_rx4_regulators, > + .num_regulators = ARRAY_SIZE(glymur_tcsr_tx1_rpt34_rx4_regulators), > }, > [TCSR_USB2_2_CLKREF_EN] = { > .name = "tcsr_usb2_2_clkref_en", > .offset = 0x70, > + .regulator_names = glymur_tcsr_tx1_rpt01_rx1_regulators, > + .num_regulators = ARRAY_SIZE(glymur_tcsr_tx1_rpt01_rx1_regulators), > }, > [TCSR_USB2_3_CLKREF_EN] = { > .name = "tcsr_usb2_3_clkref_en", > .offset = 0x74, > + .regulator_names = glymur_tcsr_tx1_rpt34_rx4_regulators, > + .num_regulators = ARRAY_SIZE(glymur_tcsr_tx1_rpt34_rx4_regulators), > }, > [TCSR_USB2_4_CLKREF_EN] = { > .name = "tcsr_usb2_4_clkref_en", > .offset = 0x88, > + .regulator_names = glymur_tcsr_tx1_rpt34_rx4_regulators, > + .num_regulators = ARRAY_SIZE(glymur_tcsr_tx1_rpt34_rx4_regulators), > }, > [TCSR_USB3_0_CLKREF_EN] = { > .name = "tcsr_usb3_0_clkref_en", > .offset = 0x64, > + .regulator_names = glymur_tcsr_tx1_rpt34_rx4_regulators, > + .num_regulators = ARRAY_SIZE(glymur_tcsr_tx1_rpt34_rx4_regulators), > }, > [TCSR_USB3_1_CLKREF_EN] = { > .name = "tcsr_usb3_1_clkref_en", > .offset = 0x68, > + .regulator_names = glymur_tcsr_tx1_rpt34_rx4_regulators, > + .num_regulators = ARRAY_SIZE(glymur_tcsr_tx1_rpt34_rx4_regulators), > }, > [TCSR_USB4_1_CLKREF_EN] = { > .name = "tcsr_usb4_1_clkref_en", > .offset = 0x44, > + .regulator_names = glymur_tcsr_tx0_rx5_regulators, > + .num_regulators = ARRAY_SIZE(glymur_tcsr_tx0_rx5_regulators), > }, > [TCSR_USB4_2_CLKREF_EN] = { > .name = "tcsr_usb4_2_clkref_en", > .offset = 0x5c, > + .regulator_names = glymur_tcsr_tx1_rpt01_rx1_regulators, > + .num_regulators = ARRAY_SIZE(glymur_tcsr_tx1_rpt01_rx1_regulators), > }, > }; >