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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?WohRzO2nnFnv5lORd84x+gGUAzm0RjegsWsS6IrHQII2DoDyKf65RyysmiSD?= =?us-ascii?Q?tBeyURbOAncI3EFALKMbBjNTWSh63s+mwDj+cbcAOR5qZBe2aH0Lbc4FDoNF?= =?us-ascii?Q?Jgin/2MJgivOWQzrcFNKUPQTBeJ4XChpLQsX5DTyFPL2moHkpyrKedJcNqS5?= =?us-ascii?Q?NjbvCEYVTj33QSatgawRbr/8fPhPJbFP7W6Coh1H1IJEOvd/58rBrG87cS5E?= =?us-ascii?Q?/MZZ16uV42dOdbMtz/+1ToLjlgAuR5qI3jD3nnE3E5kUqg1ui2wt100+rMiL?= =?us-ascii?Q?locegmzNgT4hL/gFW2L6GmfNKhqOYKKcGRpBRZ+n1I/PHllPT3o3lgTI4leo?= =?us-ascii?Q?WDu7TE684vsCI57+2o593KzJcm8GOW8lrbpjgbSfVPXebcInOaeuWKsnStWT?= =?us-ascii?Q?28DXDv1h9YRCPJSrGuZvv2eTRw8B7EjIblWTfTrAI83a6QuhaMbL5bYUXkZM?= =?us-ascii?Q?H88aent5j4GAvfLfhviavWmyxCF+pDBUPDlDHcS3QisPuJVdWcrBx4H81pJV?= =?us-ascii?Q?WK+GD8OyfSNzRPmbioT9BHz6VxKffKNJ5GEJRgsW0HKG5uCLt6pa8G+OFsLF?= =?us-ascii?Q?T/E/YdxeQqSY8FIsuroFaFLnRmrC+aloGEApsXOMtad9oj3yMru69preVtQt?= =?us-ascii?Q?zgbmUSPHtVSwnM6RCuo2Q36sAH3DQU87C6Yd7RMAGjZPd5od+PULZJSVS5jm?= =?us-ascii?Q?u8bLfJL2F62nixy5u3LfUinO4P+du4xHkJrWVFCm961tFlovrkgownvifyaL?= =?us-ascii?Q?Tn4zAQmlRDrn+DprmQEGThJ0fGYM/0MOwgAU0AXMkjyH9sH5LEI9wktmUhuD?= =?us-ascii?Q?8OHDVdrNP0p/O+ZW73iwMJOGq3ZJoUAaboo57Pzke2Oj0UYDJFa5poWhuIMz?= =?us-ascii?Q?9mxcf3j+l66t8OPq0ZEqbibNP2v7qG12KWsYaY6RlCFlusGr3D8cTnOCxb7t?= =?us-ascii?Q?0VhTNlhAKYm3BMyOoicv/Uxz3jxordSXjWYqWi5otdrRQbxb8UaJV4I9sPda?= =?us-ascii?Q?bzUzxjws/VZ9+L1x38fC3UTWOFH/Q3XY08L7cMKKfZeq1ZOmfbPUMVuxd8vB?= =?us-ascii?Q?ZiXkEy8jeIYOvitKMR0Cfvh8V7ei3LWPjZl6FVLmwHOy+gfCDKGc5vkysnBm?= =?us-ascii?Q?ri7BRecI4mJq38HPDj+tMtmrzOW2wXt5hiKfULPtqtbjsJIduqSWujIV5Plq?= =?us-ascii?Q?V4FpOyxsXpHxIvccLoCK6z3ki6hZCIFaTMON5mClrRx60XPMkwhKxMHitrbf?= =?us-ascii?Q?yvZyMLh8Y+uyRTGnJSHA2ousdK7gxibSzFsrWbwHbOrWBEguKWnbLa2KA2p4?= =?us-ascii?Q?iJbA3ucv2tEDEK2vgnUM5h1AI+DJiyo4Ux+KhMMjzyB+IohcB/UkTnIOG1FN?= =?us-ascii?Q?1AmlIbKz4ni+4Ivg/AKIWSnuca71kFeArc8cHZqAb+S2GeYvfcv6gg5Qhe4k?= =?us-ascii?Q?XjS/V9oJPDBY93dqX1TcYNPs7yrtJkVMQ4ImaofbqtaDxu5YdyDYt7AgvvRX?= =?us-ascii?Q?7uy04g6+XZUX2xFh+jF1SohywZdiu/dMvBMGYU2UW+dZCvzhYejIPMcw0/rW?= =?us-ascii?Q?4cUwZqmkeILd6iUrCuOAg/Neejy6/pQwCqDRmlaBt334RDQAWge9mI5EvS/H?= =?us-ascii?Q?bC5nrLMB2gVI/RyZOIiGHxlM1OFOuw7SUkHzBLxLyeYWZiTq9NmA/1uHfa+m?= =?us-ascii?Q?92M3xUuC1t+X7qiYDM0iQVET6WmR9uEcyA3aC2xnrsw6u/Cu?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 236d8075-bb3e-4f9d-c7fc-08dec1b90bd9 X-MS-Exchange-CrossTenant-AuthSource: PA4PR04MB9366.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Jun 2026 21:42:44.6363 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: xaQ3md/OyyYU0WdvUHI+nEiH0IWvSE1rL5k1dIv6H2iRke/BChSqwf4k6DheIXuSz6XonphbAt5twK+ynS/EGA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR04MB8347 On Wed, Jun 03, 2026 at 01:30:40AM +0200, David Heidelberg wrote: > So far, only D-PHY mode was supported, which uses even bits when enabling > or masking lanes. For C-PHY configuration, the hardware instead requires > using the odd bits. > > Since there can be unrecognized configuration allow returning failure. > > Reviewed-by: Bryan O'Donoghue > Acked-by: Cory Keitz > Reviewed-by: Bryan O'Donoghue Suppose two Bryan is the same person? > Signed-off-by: David Heidelberg > --- > .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 39 +++++++++++++++++----- > 1 file changed, 31 insertions(+), 8 deletions(-) > > diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c > index dac8d2ecf7995..15876eb973718 100644 > --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c > +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c > @@ -9,16 +9,17 @@ > */ > > #include "camss.h" > #include "camss-csiphy.h" > > #include > #include > #include > +#include > > #define CSIPHY_3PH_LNn_CFG1(n) (0x000 + 0x100 * (n)) > #define CSIPHY_3PH_LNn_CFG1_SWI_REC_DLY_PRG (BIT(7) | BIT(6)) > #define CSIPHY_3PH_LNn_CFG2(n) (0x004 + 0x100 * (n)) > #define CSIPHY_3PH_LNn_CFG2_LP_REC_EN_INT BIT(3) > #define CSIPHY_3PH_LNn_CFG3(n) (0x008 + 0x100 * (n)) > #define CSIPHY_3PH_LNn_CFG4(n) (0x00c + 0x100 * (n)) > #define CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS 0xa4 > @@ -1108,23 +1109,32 @@ static void csiphy_gen2_config_lanes(struct csiphy_device *csiphy, > writel_relaxed(val, csiphy->base + r->reg_addr); > if (r->delay_us) > udelay(r->delay_us); > } > } > > static u8 csiphy_get_lane_mask(struct csiphy_lanes_cfg *lane_cfg) > { > - u8 lane_mask; > - int i; > + u8 lane_mask = 0; > > - lane_mask = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE; > + switch (lane_cfg->phy_cfg) { > + case V4L2_MBUS_CSI2_CPHY: > + for (int i = 0; i < lane_cfg->num_data; i++) > + lane_mask |= BIT(lane_cfg->data[i].pos + 1); > + break; > + case V4L2_MBUS_CSI2_DPHY: > + lane_mask = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE; > > - for (i = 0; i < lane_cfg->num_data; i++) > - lane_mask |= 1 << lane_cfg->data[i].pos; > + for (int i = 0; i < lane_cfg->num_data; i++) > + lane_mask |= BIT(lane_cfg->data[i].pos); suggest small tuning to move common logic out of switch switch (lane_cfg->phy_cfg) { case V4L2_MBUS_CSI2_CPHY: off = 1; lane_mask = 0; case V4L2_MBUS_CSI2_DPHY: off = 0; lane_mask = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE; } for (int i = 0; i < lane_cfg->num_data; i++) lane_mask |= BIT(lane_cfg->data[i].pos+ off); the same as below block Frank > + break; > + default: > + break; > + } > > return lane_mask; > } > > static bool csiphy_is_gen2(u32 version) > { > bool ret = false; > > @@ -1155,19 +1165,32 @@ static void csiphy_lanes_enable(struct csiphy_device *csiphy, > struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg; > struct csiphy_device_regs *regs = csiphy->regs; > u8 settle_cnt; > u8 val; > int i; > > settle_cnt = csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate); > > - val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE; > - for (i = 0; i < c->num_data; i++) > - val |= BIT(c->data[i].pos * 2); > + val = 0; > + > + switch (c->phy_cfg) { > + case V4L2_MBUS_CSI2_CPHY: > + for (i = 0; i < c->num_data; i++) > + val |= BIT((c->data[i].pos * 2) + 1); > + break; > + case V4L2_MBUS_CSI2_DPHY: > + val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE; > + > + for (i = 0; i < c->num_data; i++) > + val |= BIT(c->data[i].pos * 2); > + break; > + default: > + WARN_ONCE(1, "Unsupported bus type %d!\n", c->phy_cfg); > + } > > writel_relaxed(val, csiphy->base + > CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 5)); > > val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B; > writel_relaxed(val, csiphy->base + > CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 6)); > > > -- > 2.53.0 >