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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?zVr+t7iwLdkUrcuzJuVooljl6teS+HXD1/9HE9qkZ7okV7dkjI4818a53605?= =?us-ascii?Q?3lWhkiHervDWotsIlxUSs8IXZoVMTTKUQnicpoUQ+YSNnxll/o4yFV87B5Ad?= =?us-ascii?Q?3JfWj9yEbd7VpwZMoVqc/V0KgREw8LEvWlog/opLd+6Uo8DU46jDgc7DX+Us?= =?us-ascii?Q?skA1ZOsNPFuxvU8GtT9/XNJDqqcyR2K7pG6fqf9VI1br2+YgX2dBMiS+nT+h?= =?us-ascii?Q?xb0SnwIviRwM1TA0/d5cPdGAJ8QaKFiKgUVn/yzK/vFIIdJBNi5l6iXgCPap?= =?us-ascii?Q?roScWM+4rPVCag+U6+HgBRNHHmoLuXi3NLmNkMqSJpkEmvmznqkc6P28nB2f?= =?us-ascii?Q?B5yP1JxLolyurURbzg1jiotKLjtS2Kfm6QVprkpr9Lkv8VSR7TxQ1BaLxFyG?= =?us-ascii?Q?DMXKbaVu2niE2z2whOgDfUz4Q33LmNlPm70kRXtaW4JXJI/RuqlGNzhYh4jS?= =?us-ascii?Q?0SddPQMxFygr/VDVWvafFHbbD/KWKACszC9Z0O3bPVJSpF5K1A3b4dejEHBR?= =?us-ascii?Q?TVuSjaebd0v8jeVVTAaWFNHmNxMg3fI6m6pfuTvW2kVgeEyP8nVyVFdtt72/?= =?us-ascii?Q?TK7OKfeMYLPtKZLMJ578XWlg4qEVvL6DLVQ3C26sg0w0hRGyf4L+4hiqZolN?= =?us-ascii?Q?bieXT9qKtpdpR0Uy8bf6S3mzy5HOPWnnpD9TxFEXO3jKUHw+c0xCdKUdKyp1?= =?us-ascii?Q?w4MCrfQW87cPJemJqukPNtkhRsrfVDeHF+n13R+jCwYPwoenFEDBDuPj2dVT?= =?us-ascii?Q?iK1e1U5kn3FwSnEsj9xjPD6urVHGXSv50theQjAh5J5vclp/E6dAvcoyKFnv?= =?us-ascii?Q?pqoPXNSy1+8M5rroZUDV8AHacSMXNaz6mMNIEBL24rEEVOMNGx1RDEy2W8PH?= =?us-ascii?Q?G17pIu8p3Js2yMR2nRi1giRrxC6ffGF+fYsg5M+GpQhO/SkXME123vbZ2KY3?= =?us-ascii?Q?S7siiqMvNGV66l2/gqwFaD7AYsdYVUqRYL9EQbFRG+QATW3JHGqweiR9tEmS?= =?us-ascii?Q?xYrMiVIdoM8EYoTYdPWMNNjE8HDNJf4OCFl3xzEsvPI6UYmmnYVFVPTKoIzs?= =?us-ascii?Q?YMx4FyoHMUnZjdZ6k1Bwn4HzXL0+vT8WG6ZXcK0tEwE8i/K5aYGn6Od9aNAn?= =?us-ascii?Q?bK1WQFEdKs1JvGCmM6XHNtbGU1Cy0xOFTrkFQky+onK/vZPCEW/sqrkDu5Mn?= =?us-ascii?Q?RizodcFYW1PsZ3aEcakBIrWp+x83OCOk1IwaJmqxu7+vHuQZtmUlSOhqG4x7?= =?us-ascii?Q?XE10JAianoZQAVuIHREpMKbP5dOZHpBuEhqDP79VDPftNayqaUc6St7AbwR4?= =?us-ascii?Q?HsjvX9aFemhIJXC3/cI7ZOAYIa9+I4Ys75euKB5y1BLJP2CjO+d00W5ozAXg?= =?us-ascii?Q?LET7YaLn1/6d2jgNScFOMVGbUY8Mg7lclagKQPkRT5BILEaUWu7T9bkeurrl?= =?us-ascii?Q?rvDYhg3hc8KweXPxOlQ9UJLFE6mA2iNDF4pertw27neMaPjoSBpIab1kuczK?= =?us-ascii?Q?p4k2+F7kN5HPDkNZBU3vOEMNg54zYnBjF6TGqr++MYzxybF8QB8gPQtJTErS?= =?us-ascii?Q?BIftwWZNjGdIi4IY7F1ojtmqzAn81VhieH9VfD0vVV//PJGkVGM9WszXSVEM?= =?us-ascii?Q?GVS32R32lE68azR5XSChCw99yVWImu92vk/WenFaDt+669PZkSVfAQ4UGFGc?= =?us-ascii?Q?Wc57E2vN1ci25XHdhyjTlAOvik7nRWO1DEVsgMoxuBmQCtLjempzFSjZv9OP?= =?us-ascii?Q?pgeZaGas4w=3D=3D?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5b4f8d45-6f76-46d7-76c7-08dec1b9fa0e X-MS-Exchange-CrossTenant-AuthSource: PA4PR04MB9366.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Jun 2026 21:49:24.2890 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: YY6UYHsYqBeb7FP6pmnSbtC7+s/QVx6YCNQAPo0cQNIo854XN5vC3iwDx1T6Ed1jR+iz8jkrzjBgIIOU9OWoTw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB8PR04MB6778 On Wed, Jun 03, 2026 at 01:30:42AM +0200, David Heidelberg wrote: > The lanes must not be initialized before the driver has access to > the lane configuration, as it depends on whether D-PHY or C-PHY mode > is in use. Move the lane initialization to csiphy_lanes_enable which is > called when the configuration structures are available. > > Co-developed-by: Petr Hodina > Signed-off-by: Petr Hodina > Reviewed-by: Bryan O'Donoghue > Acked-by: Cory Keitz > Signed-off-by: David Heidelberg > --- Reviewed-by: Frank Li > .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 131 +++++++++++++++------ > 1 file changed, 93 insertions(+), 38 deletions(-) > > diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c > index 15876eb973718..938c365eb352f 100644 > --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c > +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c > @@ -1163,16 +1163,108 @@ static void csiphy_lanes_enable(struct csiphy_device *csiphy, > s64 link_freq, u8 lane_mask) > { > struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg; > struct csiphy_device_regs *regs = csiphy->regs; > u8 settle_cnt; > u8 val; > int i; > > + switch (csiphy->camss->res->version) { > + case CAMSS_845: > + if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) { > + regs->lane_regs = NULL; > + regs->lane_array_size = 0; > + } else { > + regs->lane_regs = &lane_regs_sdm845[0]; > + regs->lane_array_size = ARRAY_SIZE(lane_regs_sdm845); > + } > + break; > + case CAMSS_2290: > + case CAMSS_6150: > + if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) { > + regs->lane_regs = NULL; > + regs->lane_array_size = 0; > + } else { > + regs->lane_regs = &lane_regs_qcm2290[0]; > + regs->lane_array_size = ARRAY_SIZE(lane_regs_qcm2290); > + } > + break; > + case CAMSS_6350: > + if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) { > + regs->lane_regs = NULL; > + regs->lane_array_size = 0; > + } else { > + regs->lane_regs = &lane_regs_sm6350[0]; > + regs->lane_array_size = ARRAY_SIZE(lane_regs_sm6350); > + } > + break; > + case CAMSS_7280: > + case CAMSS_8250: > + if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) { > + regs->lane_regs = NULL; > + regs->lane_array_size = 0; > + } else { > + regs->lane_regs = &lane_regs_sm8250[0]; > + regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8250); > + } > + break; > + case CAMSS_8280XP: > + if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) { > + regs->lane_regs = NULL; > + regs->lane_array_size = 0; > + } else { > + regs->lane_regs = &lane_regs_sc8280xp[0]; > + regs->lane_array_size = ARRAY_SIZE(lane_regs_sc8280xp); > + } > + break; > + case CAMSS_X1E80100: > + if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) { > + regs->lane_regs = NULL; > + regs->lane_array_size = 0; > + } else { > + regs->lane_regs = &lane_regs_x1e80100[0]; > + regs->lane_array_size = ARRAY_SIZE(lane_regs_x1e80100); > + } > + break; > + case CAMSS_8550: > + if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) { > + regs->lane_regs = NULL; > + regs->lane_array_size = 0; > + } else { > + regs->lane_regs = &lane_regs_sm8550[0]; > + regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8550); > + } > + break; > + case CAMSS_8650: > + if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) { > + regs->lane_regs = NULL; > + regs->lane_array_size = 0; > + } else { > + regs->lane_regs = &lane_regs_sm8650[0]; > + regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8650); > + } > + break; > + case CAMSS_8300: > + case CAMSS_8775P: > + if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) { > + regs->lane_regs = NULL; > + regs->lane_array_size = 0; > + } else { > + regs->lane_regs = &lane_regs_sa8775p[0]; > + regs->lane_array_size = ARRAY_SIZE(lane_regs_sa8775p); > + } > + break; > + default: > + break; > + } > + > + if (!regs->lane_regs && c->phy_cfg == V4L2_MBUS_CSI2_CPHY) > + WARN_ONCE(1, "Missing lane_regs definition for C-PHY!\n"); > + > settle_cnt = csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate); > > val = 0; > > switch (c->phy_cfg) { > case V4L2_MBUS_CSI2_CPHY: > for (i = 0; i < c->num_data; i++) > val |= BIT((c->data[i].pos * 2) + 1); > @@ -1231,63 +1323,26 @@ static int csiphy_init(struct csiphy_device *csiphy) > struct device *dev = csiphy->camss->dev; > struct csiphy_device_regs *regs; > > regs = devm_kmalloc(dev, sizeof(*regs), GFP_KERNEL); > if (!regs) > return -ENOMEM; > > csiphy->regs = regs; > - regs->offset = 0x800; > regs->common_status_offset = 0xb0; > > switch (csiphy->camss->res->version) { > - case CAMSS_845: > - regs->lane_regs = &lane_regs_sdm845[0]; > - regs->lane_array_size = ARRAY_SIZE(lane_regs_sdm845); > - break; > - case CAMSS_2290: > - case CAMSS_6150: > - regs->lane_regs = &lane_regs_qcm2290[0]; > - regs->lane_array_size = ARRAY_SIZE(lane_regs_qcm2290); > - break; > - case CAMSS_6350: > - regs->lane_regs = &lane_regs_sm6350[0]; > - regs->lane_array_size = ARRAY_SIZE(lane_regs_sm6350); > - break; > - case CAMSS_7280: > - case CAMSS_8250: > - regs->lane_regs = &lane_regs_sm8250[0]; > - regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8250); > - break; > - case CAMSS_8280XP: > - regs->lane_regs = &lane_regs_sc8280xp[0]; > - regs->lane_array_size = ARRAY_SIZE(lane_regs_sc8280xp); > - break; > case CAMSS_X1E80100: > - regs->lane_regs = &lane_regs_x1e80100[0]; > - regs->lane_array_size = ARRAY_SIZE(lane_regs_x1e80100); > - regs->offset = 0x1000; > - break; > case CAMSS_8550: > - regs->lane_regs = &lane_regs_sm8550[0]; > - regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8550); > - regs->offset = 0x1000; > - break; > case CAMSS_8650: > - regs->lane_regs = &lane_regs_sm8650[0]; > - regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8650); > regs->offset = 0x1000; > break; > - case CAMSS_8300: > - case CAMSS_8775P: > - regs->lane_regs = &lane_regs_sa8775p[0]; > - regs->lane_array_size = ARRAY_SIZE(lane_regs_sa8775p); > - break; > default: > + regs->offset = 0x800; > break; > } > > return 0; > } > > const struct csiphy_hw_ops csiphy_ops_3ph_1_0 = { > .get_lane_mask = csiphy_get_lane_mask, > > -- > 2.53.0 >