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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?N4a0Rfk6GhrXSFF7drW/3IFqeiw0fNMCQQeKmf3mcPWrtIatIwCw8qDvSTHd?= =?us-ascii?Q?PoQGrYfO7rs2tE89zVFYUzo7MXswNrbrS4HdtLIpSbZDNJMzwtJyAAkSvEmC?= =?us-ascii?Q?kaPI185ZHF5s8sBr845+n2C2UjWMClBfjvveg3EhKfQWzjOqkWrlpTyGTWrn?= =?us-ascii?Q?vOebIqw4R0cEoNi5m7MZPXW+mTTQqwjEDbV2M9VCQPJHvCk8WJycdIQcjkAT?= =?us-ascii?Q?4fSVhunINJzx8j/R4FZN2gPtmUq0q1Yjk6i6iW9ykv21+/rJtsO7Bym0l66n?= =?us-ascii?Q?7t2L7CiLyTmF6GnPZ5C4WqkRfpyI/5/SrkFnO7EJ7hPQN3BGQEnfYKb3voCq?= =?us-ascii?Q?BOnHqDDnVvupaZi/lV8B3J3X3sd4Cj2TYyvF9gMCqCYhZK3mWNh3tO4305l5?= =?us-ascii?Q?h/3mrT+0Pn1coUMcwdPqGENJW94RFSKUwhN8FqLU9OfeKy15atdgGLgc3QBE?= =?us-ascii?Q?rZY//vQ6/GHf5AAMvSEiE++8OZDnJylRy62bl0o5DMP41fK8egnWG6xNOO/U?= =?us-ascii?Q?qOxjqrkB3kr1CCvHS1EiTofKruxKuZwqe9x7hQGqbv87gU0GG0PtKmSOQEWA?= =?us-ascii?Q?EGRkKqtQGrJvtO2LSLSrIZx2GmJ3nDPVlOSFGr5GuWw8y/fFNUcDBQxzdlrY?= =?us-ascii?Q?YBzq4CTu/mM4qIL3M2dLgLQ65Jb1WctbONUp3YqoXIlXyL10QR429tS8hIDN?= =?us-ascii?Q?F4gsG+XVRcVAkG6VsZD71lZNfKyXr22IKnWBf1DCSL+Q75JoiCm0gqXK1Q5I?= =?us-ascii?Q?pdtnX5hhNP0etafmWEyjfBvizjeZdav+9GcJC/AKK240FjQURTF3khDIU+ak?= =?us-ascii?Q?Hfipw1VQ7dAa/oH64y7G4OTR51VaRQeBh0qVRRK6Me4dyIL1x4xp0ZGmNDfQ?= =?us-ascii?Q?LLBgvgqp2S+gMwPEqduTZh5l20pmnGE47EP9zs++gAfjRwNmxOUU4rKLMxx3?= =?us-ascii?Q?I3G4WM0U6TXULf4lmEQiFCoNwnX5mRKp3K2dNwhvCLezrzNAAn3bOu7V6ilk?= =?us-ascii?Q?QCZ2eOQLl6I/eTR/iKsSmSxrehWwxf/v9wJZJVWneMLA2AdrVV4a00UO9mGu?= =?us-ascii?Q?ndaRVjn0sTtnoMSzMq3UAv07tgWl3qTRk9xP3uitDUrX+Ex9f1EoZOhYJ2Rm?= =?us-ascii?Q?b2GjDNlGcDOO43Lwq291FI5rM8Dm6rqxeF/BceccPVq6aYts4eEVSlU4sYH6?= =?us-ascii?Q?RGy1fJG92qXqcGxxmCXt3yJmqyHDctkcu/QBVZM4WesSH0NYkjVoFBgCUXxY?= =?us-ascii?Q?8JocVS6rHyrrGMZhS+CWpYFSBeR1d9TDQ2jmuQPngnNB/+39HR2Soowd1pJ5?= =?us-ascii?Q?GTd7Tf9TpngGZGNc5sNgQ4RMZZo1bhCNybDVFKonfW92QHmi3gfwhYuV2vF0?= =?us-ascii?Q?Qn1Uhl91oRpyubBLcY9arlURTOTVtMeIRvTqNntRvnmcsaUeEDT1IlhxLKNA?= =?us-ascii?Q?BDYNFuXPIrQVEHpnCtz7Dh/tNuIL+gFFuYGty4Gz/6ydfMM+hfawGS3/d5FC?= =?us-ascii?Q?lJDkiFAvhgKziKRdROtb6uxbjyWJeTayK7H410nXpFY5Q1Bi4DKrmkIMzHgo?= =?us-ascii?Q?xoQh0nDCcJGexPVHSw+D9JTBdZaWLubEOxEQ05FLD24lVmWkMXTBvHgJqQQz?= =?us-ascii?Q?9v1mA4Rj5jHD1NCgwlh30m8Jgn6W8znurulWbV463kmAvh5g4AStdA4Wz4/r?= =?us-ascii?Q?fHoEpvns339vOaUEc6WGyhmm+tYfFXvBa8VcNV52pnjRMfq1?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: a63a42a7-713d-4658-0951-08dec27664ad X-MS-Exchange-CrossTenant-AuthSource: PA4PR04MB9366.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jun 2026 20:18:08.5488 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: wXnGanNaQZRXS7aHHrFDpgDxjDlpge5a2ypYKsY4T8DMcKk/w8WOYBPoZ8XBd0OPah7NPnIN5JfNZ8TiD0Ul3A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR04MB8333 On Mon, May 25, 2026 at 03:24:10PM +0900, Koichiro Den wrote: > DesignWare eDMA can signal completion locally through edma_int[] and > remotely through IMWr/MSI. When channels are delegated to a remote > frontend, the local endpoint side and the remote host side must not both > service the same DONE/ABORT status. > > Add dw_edma_irq_config, carried through dma_slave_config, so a frontend > can choose default, local, or remote IRQ handling per channel. Update the > v0 path so linked-list interrupt generation and DONE/ABORT masking follow > the selected mode. If a frontend does not supply the config, keep the > existing behavior. > > HDMA native already uses dma_slave_config.peripheral_config as an int for > non-LL mode selection. Keep that interface unchanged and reject the new > IRQ config there until an IRQ routing model is implemented and validated. > > Signed-off-by: Koichiro Den > --- ... > > +static inline bool > +dw_edma_core_ch_ignore_irq(struct dw_edma_chan *chan) > +{ > + struct dw_edma *dw = chan->dw; > + > + if (dw->chip->flags & DW_EDMA_CHIP_LOCAL) suppose it should be pre channel config, why need check chip's informaiton? > + return chan->irq_mode == DW_EDMA_CH_IRQ_REMOTE; > + else > + return chan->irq_mode == DW_EDMA_CH_IRQ_LOCAL; > +} > + > #endif /* _DW_EDMA_CORE_H */ > diff --git a/drivers/dma/dw-edma/dw-edma-v0-core.c b/drivers/dma/dw-edma/dw-edma-v0-core.c > index 69e8279adec8..08ec2bd7856e 100644 > --- a/drivers/dma/dw-edma/dw-edma-v0-core.c > +++ b/drivers/dma/dw-edma/dw-edma-v0-core.c > @@ -256,9 +256,11 @@ dw_edma_v0_core_handle_int(struct dw_edma_irq *dw_irq, enum dw_edma_dir dir, > for_each_set_bit(pos, &val, total) { > chan = &dw->chan[pos + off]; > > + if (dw_edma_core_ch_ignore_irq(chan)) > + continue; > + > dw_edma_v0_core_clear_done_int(chan); > done(chan); > - > ret = IRQ_HANDLED; > } > > @@ -267,9 +269,11 @@ dw_edma_v0_core_handle_int(struct dw_edma_irq *dw_irq, enum dw_edma_dir dir, > for_each_set_bit(pos, &val, total) { > chan = &dw->chan[pos + off]; > > + if (dw_edma_core_ch_ignore_irq(chan)) > + continue; > + > dw_edma_v0_core_clear_abort_int(chan); > abort(chan); > - > ret = IRQ_HANDLED; > } > > @@ -331,7 +335,8 @@ static void dw_edma_v0_core_write_chunk(struct dw_edma_chunk *chunk) > j--; > if (!j) { > control |= DW_EDMA_V0_LIE; > - if (!(chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL)) > + if (!(chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL) && > + chan->irq_mode != DW_EDMA_CH_IRQ_LOCAL) > control |= DW_EDMA_V0_RIE; > } > > @@ -407,10 +412,15 @@ static void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first) > break; > } > } > - /* Interrupt unmask - done, abort */ > + /* Interrupt mask/unmask - done, abort */ > tmp = GET_RW_32(dw, chan->dir, int_mask); > - tmp &= ~FIELD_PREP(EDMA_V0_DONE_INT_MASK, BIT(chan->id)); > - tmp &= ~FIELD_PREP(EDMA_V0_ABORT_INT_MASK, BIT(chan->id)); > + if (chan->irq_mode == DW_EDMA_CH_IRQ_REMOTE) { > + tmp |= FIELD_PREP(EDMA_V0_DONE_INT_MASK, BIT(chan->id)); > + tmp |= FIELD_PREP(EDMA_V0_ABORT_INT_MASK, BIT(chan->id)); > + } else { > + tmp &= ~FIELD_PREP(EDMA_V0_DONE_INT_MASK, BIT(chan->id)); > + tmp &= ~FIELD_PREP(EDMA_V0_ABORT_INT_MASK, BIT(chan->id)); > + } > SET_RW_32(dw, chan->dir, int_mask, tmp); > /* Linked list error */ > tmp = GET_RW_32(dw, chan->dir, linked_list_err_en); > diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h > index 3e15cf83b784..2bf2298711e1 100644 > --- a/include/linux/dma/edma.h > +++ b/include/linux/dma/edma.h > @@ -60,6 +60,43 @@ enum dw_edma_chip_flags { > DW_EDMA_CHIP_LOCAL = BIT(0), > }; > > +/** > + * enum dw_edma_ch_irq_mode - per-channel interrupt routing control > + * @DW_EDMA_CH_IRQ_DEFAULT: keep legacy behavior Feel like it make things complex, most likely use pcie ep probe, it should be use DW_EDMA_CH_IRQ_LOCAL. If probe from dw-edma-pcie.c, it should be use DW_EDMA_CH_IRQ_REMOTE. Add default mode, it make check logic become complex. Frank > + * @DW_EDMA_CH_IRQ_LOCAL: local interrupt only (edma_int[]) > + * @DW_EDMA_CH_IRQ_REMOTE: remote interrupt only (IMWr/MSI), > + * while masking local DONE/ABORT output. > + * > + * DesignWare EP eDMA can signal interrupts locally through the edma_int[] > + * bus, and remotely using posted memory writes (IMWr) that may be > + * interpreted as MSI/MSI-X by the RC. > + * > + * For the v0 eDMA programming path, DMA_*_INT_MASK gates the local edma_int[] > + * assertion, while there is no dedicated per-channel mask for IMWr generation. > + * To request a remote-only interrupt, Synopsys recommends setting both LIE and > + * RIE, and masking the local interrupt in DMA_*_INT_MASK (rather than relying > + * on LIE=0/RIE=1). See the DesignWare endpoint databook 5.40a, Non Linked > + * List Mode interrupt handling ("Hint"). > + */ > +enum dw_edma_ch_irq_mode { > + DW_EDMA_CH_IRQ_DEFAULT = 0, > + DW_EDMA_CH_IRQ_LOCAL, > + DW_EDMA_CH_IRQ_REMOTE, > +}; > + > +/** > + * struct dw_edma_irq_config - dw-edma interrupt routing configuration > + * @irq_mode: per-channel interrupt routing control. > + * @reserved: must be zero. > + * > + * Pass this structure via dma_slave_config.peripheral_config and > + * dma_slave_config.peripheral_size. > + */ > +struct dw_edma_irq_config { > + enum dw_edma_ch_irq_mode irq_mode; > + u32 reserved; > +}; > + > /** > * struct dw_edma_chip - representation of DesignWare eDMA controller hardware > * @dev: struct device of the eDMA controller > @@ -76,6 +113,8 @@ enum dw_edma_chip_flags { > * @db_irq: Virtual IRQ dedicated to interrupt emulation > * @db_offset: Offset from DMA register base > * @mf: DMA register map format > + * @default_irq_mode: default per-channel interrupt routing when client > + * does not supply dw_edma_irq_config > * @dw: struct dw_edma that is filled by dw_edma_probe() > */ > struct dw_edma_chip { > @@ -101,6 +140,7 @@ struct dw_edma_chip { > resource_size_t db_offset; > > enum dw_edma_map_format mf; > + enum dw_edma_ch_irq_mode default_irq_mode; suppose it is pre-channel config? Frank > > struct dw_edma *dw; > bool cfg_non_ll; > -- > 2.51.0 >