From: Frank Li <Frank.li@nxp.com>
To: Koichiro Den <den@valinux.co.jp>
Cc: Vinod Koul <vkoul@kernel.org>, Frank Li <Frank.Li@kernel.org>,
Manivannan Sadhasivam <mani@kernel.org>,
Marek Vasut <marek.vasut+renesas@mailbox.org>,
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>,
dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 04/12] dmaengine: dw-edma-pcie: Track non-LL mode in DMA data
Date: Thu, 4 Jun 2026 16:26:11 -0400 [thread overview]
Message-ID: <aiHfY2lojacQir4l@lizhi-Precision-Tower-5810> (raw)
In-Reply-To: <20260525062420.3315904-5-den@valinux.co.jp>
On Mon, May 25, 2026 at 03:24:12PM +0900, Koichiro Den wrote:
> The dw-edma-pcie driver copies static template data into a mutable
> dw_edma_pcie_data instance before applying capability-derived updates.
> Keep the derived non-LL mode in that copy as well, instead of only
> tracking it in a local variable in dw_edma_pcie_probe().
>
> This prepares for keeping capability parsing behind match data without a
> separate non-LL output parameter.
>
> No functional change intended.
>
> Suggested-by: Frank Li <Frank.Li@nxp.com>
> Signed-off-by: Koichiro Den <den@valinux.co.jp>
> ---
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> Changes in v2:
> - New patch, per Frank's feedback.
>
> drivers/dma/dw-edma/dw-edma-pcie.c | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-edma-pcie.c
> index 0b30ce138503..e92ff5dc6f67 100644
> --- a/drivers/dma/dw-edma/dw-edma-pcie.c
> +++ b/drivers/dma/dw-edma/dw-edma-pcie.c
> @@ -72,6 +72,7 @@ struct dw_edma_pcie_data {
> u16 wr_ch_cnt;
> u16 rd_ch_cnt;
> u64 devmem_phys_off;
> + bool cfg_non_ll;
> };
>
> static const struct dw_edma_pcie_data snps_edda_data = {
> @@ -312,7 +313,6 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev,
> struct dw_edma_chip *chip;
> int err, nr_irqs;
> int i, mask;
> - bool non_ll = false;
>
> struct dw_edma_pcie_data *vsec_data __free(kfree) =
> kmalloc_obj(*vsec_data);
> @@ -344,14 +344,14 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev,
> * the HDMA IP.
> */
> if (vsec_data->devmem_phys_off == DW_PCIE_XILINX_MDB_INVALID_ADDR)
> - non_ll = true;
> + vsec_data->cfg_non_ll = true;
>
> /*
> * Configure the channel LL and data blocks if number of
> * channels enabled in VSEC capability are more than the
> * channels configured in xilinx_mdb_data.
> */
> - if (!non_ll)
> + if (!vsec_data->cfg_non_ll)
> dw_edma_set_chan_region_offset(vsec_data, BAR_2, 0,
> DW_PCIE_XILINX_MDB_LL_OFF_GAP,
> DW_PCIE_XILINX_MDB_LL_SIZE,
> @@ -404,7 +404,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev,
> chip->mf = vsec_data->mf;
> chip->nr_irqs = nr_irqs;
> chip->ops = &dw_edma_pcie_plat_ops;
> - chip->cfg_non_ll = non_ll;
> + chip->cfg_non_ll = vsec_data->cfg_non_ll;
>
> chip->ll_wr_cnt = vsec_data->wr_ch_cnt;
> chip->ll_rd_cnt = vsec_data->rd_ch_cnt;
> @@ -413,7 +413,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev,
> if (!chip->reg_base)
> return -ENOMEM;
>
> - for (i = 0; i < chip->ll_wr_cnt && !non_ll; i++) {
> + for (i = 0; i < chip->ll_wr_cnt && !vsec_data->cfg_non_ll; i++) {
> struct dw_edma_region *ll_region = &chip->ll_region_wr[i];
> struct dw_edma_region *dt_region = &chip->dt_region_wr[i];
> struct dw_edma_block *ll_block = &vsec_data->ll_wr[i];
> @@ -440,7 +440,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev,
> dt_region->sz = dt_block->sz;
> }
>
> - for (i = 0; i < chip->ll_rd_cnt && !non_ll; i++) {
> + for (i = 0; i < chip->ll_rd_cnt && !vsec_data->cfg_non_ll; i++) {
> struct dw_edma_region *ll_region = &chip->ll_region_rd[i];
> struct dw_edma_region *dt_region = &chip->dt_region_rd[i];
> struct dw_edma_block *ll_block = &vsec_data->ll_rd[i];
> --
> 2.51.0
>
next prev parent reply other threads:[~2026-06-04 20:26 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-25 6:24 [PATCH v2 00/12] dmaengine: dw-edma: Prepare for PCI EP DMA (part 1/3) Koichiro Den
2026-05-25 6:24 ` [PATCH v2 01/12] dmaengine: dw-edma: Add hardware channel filter Koichiro Den
2026-06-04 20:40 ` Frank Li
2026-06-05 2:26 ` Koichiro Den
2026-05-25 6:24 ` [PATCH v2 02/12] dmaengine: dw-edma: Add per-channel interrupt routing control Koichiro Den
2026-06-04 20:18 ` Frank Li
2026-06-05 2:36 ` Koichiro Den
2026-05-25 6:24 ` [PATCH v2 03/12] dmaengine: dw-edma: Add partial channel ownership mode Koichiro Den
2026-06-04 20:24 ` Frank Li
2026-06-05 2:40 ` Koichiro Den
2026-05-25 6:24 ` [PATCH v2 04/12] dmaengine: dw-edma-pcie: Track non-LL mode in DMA data Koichiro Den
2026-06-04 20:26 ` Frank Li [this message]
2026-05-25 6:24 ` [PATCH v2 05/12] dmaengine: dw-edma-pcie: Add capability match data Koichiro Den
2026-06-04 20:28 ` Frank Li
2026-05-25 6:24 ` [PATCH v2 06/12] dmaengine: dw-edma-pcie: Rename vsec_data to dma_data Koichiro Den
2026-06-04 20:35 ` Frank Li
2026-06-05 2:42 ` Koichiro Den
2026-05-25 6:24 ` [PATCH v2 07/12] dmaengine: dw-edma-pcie: Add default IRQ mode to match data Koichiro Den
2026-05-25 6:24 ` [PATCH v2 08/12] dmaengine: dw-edma-pcie: Add platform ops " Koichiro Den
2026-06-04 20:37 ` Frank Li
2026-05-25 6:24 ` [PATCH v2 09/12] dmaengine: dw-edma-pcie: Add register offset match flag Koichiro Den
2026-05-25 6:24 ` [PATCH v2 10/12] dmaengine: dw-edma-pcie: Factor out descriptor block address lookup Koichiro Den
2026-05-25 6:24 ` [PATCH v2 11/12] dmaengine: dw-edma-pcie: Handle optional data blocks Koichiro Den
2026-05-25 6:24 ` [PATCH v2 12/12] dmaengine: dw-edma-pcie: Add chip flags to match data Koichiro Den
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