From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 0F456380FF9 for ; Fri, 5 Jun 2026 14:20:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780669214; cv=none; b=NIVMu5jyNp7eI6EU2wQoepPKtP/ONcGqBvJOtMhk2u8BT78O6G8rmVk7ATy5GupgLsqVGrmkswFrbIlnnVJ7nXUsR5akMf9sg5TCDHPx8c2uxsiiq6HCCcoH6SYrO3bVyP1tZUXfAdcF00hbBMvYTiZwdhsNOGmzYLf9auMNP+M= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780669214; c=relaxed/simple; bh=WKtWN3MR+ErhcemB5UOy69xqNA7Dq7bg3jg3xIocdnI=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=D0Fqdt8RdSsssDToS8424Ilsvp5Ahsuo/RMgsEcGtM6EJYFLB6ZoVM38a3WYBroP4sEBa0pOYp8Bzhhu2bTG+oR/hwlPJBtByDnwOBdmPKc26tsY2R2cI0gPx3kRh1oT5Si/LHxYb5lTGqXLYXyPsCh514OGZqfC6dfZTFl+d0I= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=K0/+rTQ+; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="K0/+rTQ+" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 44B184D1B for ; Fri, 5 Jun 2026 07:20:01 -0700 (PDT) Received: from [192.168.0.1] (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id EFE963FAF5 for ; Fri, 5 Jun 2026 07:20:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1780669206; bh=WKtWN3MR+ErhcemB5UOy69xqNA7Dq7bg3jg3xIocdnI=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=K0/+rTQ+Ztg8hnyqiXZQgYikQc6FsJPWqqEl8hleea6jjEvVosP81GYjX2phG+AFZ utM3e2y7WFPBNCTXHi4W68Fu4RlEXVCIQmoIAlsBaEvnf7UVPzhLcTKhd6PGFW9fCR AkeDQ872IHgIRUWvbZqQNmpkP1dHiUho2br+w7Rs= Date: Fri, 5 Jun 2026 15:20:00 +0100 From: Liviu Dudau To: Gustavo Kenji =?utf-8?B?TWVuZG9uw6dh?= Kaneko Cc: dri-devel@lists.freedesktop.org, airlied@gmail.com, simona@ffwll.ch, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/2] drm/arm/malidp: fix ignored clk_prepare_enable() in runtime PM resume Message-ID: References: <20260531052945.65117-1-kaneko.dev@pm.me> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20260531052945.65117-1-kaneko.dev@pm.me> On Sun, May 31, 2026 at 05:29:57AM +0000, Gustavo Kenji Mendonça Kaneko wrote: > malidp_runtime_pm_resume() calls clk_prepare_enable() three times > without checking the return value. If any clock fails to enable, the > driver silently proceeds with unclocked hardware, leading to undefined > behavior. > > Use clk_bulk_prepare_enable() which atomically enables all clocks and > automatically rolls back successfully enabled clocks on failure. This > is consistent with how the suspend path already uses > clk_bulk_disable_unprepare() in malidp_runtime_pm_suspend(). I can't see where you can find other calls to clk_buld_xxxx() in the malidp code. What sort of code review have you done here? Best regards, Liviu > > This issue was found by code review without access to Mali DP hardware. > > Signed-off-by: Gustavo Kenji Mendonça Kaneko > --- > drivers/gpu/drm/arm/malidp_drv.c | 13 ++++++++++--- > 1 file changed, 10 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/arm/malidp_drv.c b/drivers/gpu/drm/arm/malidp_drv.c > index b765f6c9eea4..1e4336c3a2fa 100644 > --- a/drivers/gpu/drm/arm/malidp_drv.c > +++ b/drivers/gpu/drm/arm/malidp_drv.c > @@ -689,10 +689,17 @@ static int malidp_runtime_pm_resume(struct device *dev) > struct drm_device *drm = dev_get_drvdata(dev); > struct malidp_drm *malidp = drm_to_malidp(drm); > struct malidp_hw_device *hwdev = malidp->dev; > + struct clk_bulk_data clks[] = { > + { .clk = hwdev->pclk }, > + { .clk = hwdev->aclk }, > + { .clk = hwdev->mclk }, > + }; > + int err; > + > + err = clk_bulk_prepare_enable(ARRAY_SIZE(clks), clks); > + if (err) > + return err; > > - clk_prepare_enable(hwdev->pclk); > - clk_prepare_enable(hwdev->aclk); > - clk_prepare_enable(hwdev->mclk); > hwdev->pm_suspended = false; > malidp_de_irq_hw_init(hwdev); > malidp_se_irq_hw_init(hwdev); > -- > 2.54.0 > > -- ==================== | I would like to | | fix the world, | | but they're not | | giving me the | \ source code! / --------------- ¯\_(ツ)_/¯