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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?8AJDFhCn4UnlSJxAEHHAbQA8s1ogQtVVeg5P8K8BBPnzkCtQipRmStmXC/kk?= =?us-ascii?Q?TLi2UOE07uVMpnSHB6R/soBAzCC0KQPsR7BBbahVjKLrFvcSEn2eB9WGSBvx?= =?us-ascii?Q?1ImwbZVU8MGxS9hQ8R6QSSi+uoa0ckfXcMmfkYVXLfBiPkXgwj8vYRiUzIbj?= =?us-ascii?Q?4LwYT3MHONaduR9oRKUEDYZE1DdeV2NvD1ixd0Z8ytHv/+2AnKnPiJW/52Wk?= =?us-ascii?Q?JHcuAlTCSemt2HAZIhbnPH9qOjVKN2zuEabWkfhebErMIFVPZJeNu3RwQILG?= =?us-ascii?Q?Fwt3588VcsZ5Hv8Yw1fJFShh3+wn56hpX8T9lgITUd+7DdYL8q+F19m0I1Cm?= =?us-ascii?Q?yM+YCqMIql8iEqUmBGXxnhOaJsfpEOu3eV6fv/cl5sm7Wb6L2g2AGbMh0m96?= =?us-ascii?Q?QJ4JOtVWzmtfuDNe3GFWVSYHtGKVDdaPc84fxbYjhnj88pfKQUU6mupJ4k/L?= =?us-ascii?Q?ji2GtMtdUWfOrbZt4OCODYsp/FhkI7fFDijBNbFTkk9m94fPzkYpJJ/46Fj1?= =?us-ascii?Q?2/3zi7iBUNBftlcVeJH1bHZAnZkucd3wtYMIRgk5VX79Emdv9QToLciNVWyG?= =?us-ascii?Q?x8ZYCKk7tPDPUOzaTGzCVXagYVDqzF2FaGdQ4L3/dBUBWBjl/abVpzTDNpzh?= =?us-ascii?Q?alV1zbLCnRDey2j6zQCkIAy9QmjPig3o9jcF3q3TtM6Aazam9m2+1MwiuCEM?= =?us-ascii?Q?IdlOcBlIOlsUhlkPyNz9Mjf3Mb7mK6el0QeGBXwW1VAhH1VhnWKBdMDNfR1W?= =?us-ascii?Q?5fMw7wyGhigjkNHFOO5VyvzR6/auLCZeEwFJdNhGOsTZ0YU9iiir+kSs1p9b?= =?us-ascii?Q?qyRmeLpWQt54MQ/qJB7NoaAuAucKvjwelowI2Lvlo6lTepBGaBC/u1YDQCK5?= =?us-ascii?Q?+A3tPEsNr2RruvuWkLaPeW0hkSosgfVbb5mpr2EA5gfLK6OymMHOAZnqxBKP?= =?us-ascii?Q?oiKoMjzVKvPJ9X2Nuj6E2CrGwoB49vSZCVp2CSthKB2lEBNgJbzzAj0laww+?= =?us-ascii?Q?j8PaV+bmHXFiHbbx3RrAO17ShaufOuKl0d703L+IX3jbTFq6gqSwxLmNbWr9?= =?us-ascii?Q?PkLmzz7Fyn+HNidPo5RME4duX4n64Y9ZWYh36tVtVInmIxMNYccbxuk9l/7q?= =?us-ascii?Q?gFouDuAWgLP54rTo9+DozqKZdWt3h7FItOFOk0rgFfUbI9wLGraBhkkVIlTb?= =?us-ascii?Q?F1wM9ZAaNuoUAypzFRjebrOhnSiBRA7ZUVsYVlDoFpx2zlOl/QqpD1MhU7tF?= =?us-ascii?Q?4AVxuveccxTnfzs2TtcV1+mOP056jwfC6wKhRVNuGIHHCgtnmfUOPacZVS8n?= =?us-ascii?Q?J3Ddg2UMkcnAeIIyM+WBQnkOijXqbWoeCYib9cKmJSh5iLYE1/ws1ujE79tc?= =?us-ascii?Q?A0bpUCzDFRSZu5UV/IQKYwsM7dx6aVn7yMkq+R4ymRa5QrQCo7+GbAnCS1X7?= =?us-ascii?Q?gqHjdOayUEVhMOQCPAQVYLS3eejyVeyHHDOxipTjtQo7HIHuLS/Wc7djB4SR?= =?us-ascii?Q?ePV82MCXQp33KRBi0hCVmNGZrLnjhYamoDIXI0wtupvyFDnSDjgM7SZnKUJU?= =?us-ascii?Q?iMQ93/bbaDZmDW8Gh3Tvxh9C6y7ghIM0CccqgME7d1Y+EugiA8+0V8gkQIep?= =?us-ascii?Q?e32XuA2dLLKpuhFi7Qmhe6aiA6bHM3ALcJ5O4sztdYtajgdatyTDnDB447+4?= =?us-ascii?Q?qBvtGI80L9w0VAvY1eOvhFCitBz+1uC81KjVvZihUwCA8bVxZHcIz5seJK5W?= =?us-ascii?Q?FC1dDm9vYg=3D=3D?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 986d0136-085b-4bc7-21fe-08dec32e79fd X-MS-Exchange-CrossTenant-AuthSource: PA4PR04MB9366.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jun 2026 18:15:57.6885 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: H8QVAFpLXD3D811lMaKirct8bpyX4QHTj7jVmDvMLJfZmU/+xVvFbqqVC2bWEWvIAGzc3eR7XEe/61iDzmB/aQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR04MB7991 On Fri, Jun 05, 2026 at 11:48:05AM +0000, Verma, Devendra wrote: > Public > > > -----Original Message----- > > From: Frank Li > > Sent: Friday, June 5, 2026 01:28 > > To: Verma, Devendra > > Cc: bhelgaas@google.com; mani@kernel.org; vkoul@kernel.org; > > Frank.Li@kernel.org; dmaengine@vger.kernel.org; linux- > > kernel@vger.kernel.org; Simek, Michal > > Subject: Re: [PATCH v3] dmaengine: dw-edma: Enable HDMA 64R/W > > Channels > > > > On Wed, Jun 03, 2026 at 08:11:47PM +0530, Devendra K Verma wrote: > > > As per 'Designware Cores PCI Express Controller Databook', Section 7.1 > > > - Overview, HDMA supports 64 Read and 64 Write channels. Current > > > controller driver supports up to 8 read and write channels only. In > > > order to utilize all the channels the controller driver need to have > > > the channel related structs and variables as per the number of > > > channels supported by IP. > > > Following changes are made to enable 64 Read / 64 Write channel > > > support: > > > > > > o Defined HDMA specific macros to reflect the channel count. > > > o The count of ll_regions and dt_regions in dw_edma_chip and > > > dw_edma_pcie_data shall be in accordance to number of read > > > and write channels. > > > o In dw_edma_probe() configure the channels as per the channels > > > of the IP used. > > > o Changed mask types to u64 for higher channel counts. > > > > > > Signed-off-by: Devendra K Verma > > > --- > > > Changes in v2: > > > o Fixed the pre-existing bug related to GET_CH_32 > > > interchanging the channel direction and id. > > > This bug was not caused by any version of this patch. > > > o Fixed the issue when using for_each_set_bit() for mask > > > of u64 type. > > > > > > Changes in v1: > > > o On review recommendation of sashiko bot, in the function > > > dw_hdma_v0_core_off(), the loop iterates over registers > > > as per the number of channels enabled and not on total > > > number of channels supported. > > > o Changed mask types to u64 for higher channel counts. > > > --- > > ... > > > +++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c > > > @@ -53,13 +53,24 @@ __dw_ch_regs(struct dw_edma *dw, enum > > dw_edma_dir > > > dir, u16 ch) static void dw_hdma_v0_core_off(struct dw_edma *dw) { > > > int id; > > > + enum dw_edma_dir dir; > > > + > > > + dir = EDMA_DIR_WRITE; > > > + for (id = 0; id < dw->wr_ch_cnt; id++) { > > > + SET_CH_32(dw, dir, id, int_setup, > > > + HDMA_V0_STOP_INT_MASK | > > HDMA_V0_ABORT_INT_MASK); > > > + SET_CH_32(dw, dir, id, int_clear, > > > + HDMA_V0_STOP_INT_MASK | > > HDMA_V0_ABORT_INT_MASK); > > > + SET_CH_32(dw, dir, id, ch_en, 0); > > > + } > > > > > > - for (id = 0; id < HDMA_V0_MAX_NR_CH; id++) { > > > - SET_BOTH_CH_32(dw, id, int_setup, > > > - HDMA_V0_STOP_INT_MASK | > > HDMA_V0_ABORT_INT_MASK); > > > - SET_BOTH_CH_32(dw, id, int_clear, > > > - HDMA_V0_STOP_INT_MASK | > > HDMA_V0_ABORT_INT_MASK); > > > - SET_BOTH_CH_32(dw, id, ch_en, 0); > > > + dir = EDMA_DIR_READ; > > > + for (id = 0; id < dw->rd_ch_cnt; id++) { > > > + SET_CH_32(dw, dir, id, int_setup, > > > + HDMA_V0_STOP_INT_MASK | > > HDMA_V0_ABORT_INT_MASK); > > > + SET_CH_32(dw, dir, id, int_clear, > > > + HDMA_V0_STOP_INT_MASK | > > HDMA_V0_ABORT_INT_MASK); > > > + SET_CH_32(dw, dir, id, ch_en, 0); > > > > why SET_BOTH_CH_32 not work for 64 channel? > > > > SET_BOTH_CH_32 works, but this needs to be done on the channels enabled for the IP. > HDMA supports maximum of 64 channels. So if some IP enables 8 or fewer read / write channels only then the number of channels come from dw->wr_ch_cnt and dw->rd_ch_cnt. Now the logic is derived by individual read & write enabled channel count. Earlier, it was assumed that user will enable max of 8 channels which would have worked well using SET_BOTH_CH_32() but as the channels grow, the assumption that equal number of read / write channels and that they are set to max count are enabled might not hold true. Make sense, please wrap your reply, it is hard to read > > - Devendra > > > > } > > > } > > > > > > @@ -79,7 +90,7 @@ static enum dma_status > > dw_hdma_v0_core_ch_status(struct dw_edma_chan *chan) > > > u32 tmp; > > > > > > tmp = FIELD_GET(HDMA_V0_CH_STATUS_MASK, > > > - GET_CH_32(dw, chan->id, chan->dir, ch_stat)); > > > + GET_CH_32(dw, chan->dir, chan->id, ch_stat)); > > > > why need swtich id and dir here ? > > > > Frank > > This is the correct order of arguments to the GET_CH_32. The second & third arguments shall be direction and channel_id respectively. It is a pre-existing issue reported by AI bot. AI found existing problem, need seperate patch to fix it. Frank