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No byte-lane adjustment is > needed - applying the XOR causes writes to target incorrect registers > (e.g., writing to CERR at 0x401D would actually access SSRT at 0x401E). > > Set this flag in the MCF eDMA driver to bypass the XOR adjustment and > access registers at their documented addresses. > > Signed-off-by: Jean-Michel Hautbois > --- > drivers/dma/fsl-edma-common.h | 5 ++++- > drivers/dma/mcf-edma-main.c | 2 +- > 2 files changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h > index abc8f7805515..64b537527291 100644 > --- a/drivers/dma/fsl-edma-common.h > +++ b/drivers/dma/fsl-edma-common.h > @@ -225,6 +225,8 @@ struct fsl_edma_desc { > #define FSL_EDMA_DRV_TCD64 BIT(15) > /* All channel ERR IRQ share one IRQ line */ > #define FSL_EDMA_DRV_ERRIRQ_SHARE BIT(16) > +/* MCF eDMA: Different register layout, no XOR for byte access */ > +#define FSL_EDMA_DRV_MCF BIT(17) > > > #define FSL_EDMA_DRV_EDMA3 (FSL_EDMA_DRV_SPLIT_REG | \ > @@ -419,7 +421,8 @@ static inline void edma_writeb(struct fsl_edma_engine *edma, > u8 val, void __iomem *addr) > { > /* swap the reg offset for these in big-endian mode */ > - if (edma->big_endian) I think native endian, needn't set big_endian. Does it work if don't set big_endian for MCF54418? Frank > + /* MCF eDMA has different register layout, no XOR needed */ > + if (edma->big_endian && !(edma->drvdata->flags & FSL_EDMA_DRV_MCF)) > iowrite8(val, (void __iomem *)((unsigned long)addr ^ 0x3)); > else > iowrite8(val, addr); > diff --git a/drivers/dma/mcf-edma-main.c b/drivers/dma/mcf-edma-main.c > index 9e1c6400c77b..f95114829d80 100644 > --- a/drivers/dma/mcf-edma-main.c > +++ b/drivers/dma/mcf-edma-main.c > @@ -145,7 +145,7 @@ static void mcf_edma_irq_free(struct platform_device *pdev, > } > > static struct fsl_edma_drvdata mcf_data = { > - .flags = FSL_EDMA_DRV_EDMA64, > + .flags = FSL_EDMA_DRV_EDMA64 | FSL_EDMA_DRV_MCF, > .setup_irq = mcf_edma_irq_init, > }; > > > -- > 2.39.5 >