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Current controller driver supports up to 8 read and > write channels only. In order to utilize all the channels the > controller driver need to have the channel related structs > and variables as per the number of channels supported by IP. > Following changes are made to enable 64 Read / 64 Write > channel support: > > o Defined HDMA specific macros to reflect the channel count. > o The count of ll_regions and dt_regions in dw_edma_chip and > dw_edma_pcie_data shall be in accordance to number of read > and write channels. > o In dw_edma_probe() configure the channels as per the channels > of the IP used. > o Changed mask types to u64 for higher channel counts. > > Signed-off-by: Devendra K Verma > --- ... > > @@ -118,7 +129,8 @@ dw_hdma_v0_core_handle_int(struct dw_edma_irq *dw_irq, enum dw_edma_dir dir, > unsigned long total, pos, val; > irqreturn_t ret = IRQ_NONE; > struct dw_edma_chan *chan; > - unsigned long off, mask; > + unsigned long off; > + u64 mask; > > if (dir == EDMA_DIR_WRITE) { > total = dw->wr_ch_cnt; > @@ -130,7 +142,11 @@ dw_hdma_v0_core_handle_int(struct dw_edma_irq *dw_irq, enum dw_edma_dir dir, > mask = dw_irq->rd_mask; > } > > - for_each_set_bit(pos, &mask, total) { > + while (mask) { can you use DECLARE_BITMAP(status_mask, 64); and keep original for_each_set_bit() ref: https://lore.kernel.org/dmaengine/aj1JrufD1vIZH06s@lizhi-Precision-Tower-5810/T/#u Frank