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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: WwQ1a9SIjrzzREkJm+QZk5DKtpqpmzaCV7ePGh3qeOexjcLYhJ6sTIc6iZfRs7zhCRAA6D0B6V/iizX8DH0nzghasnvE23UlmW1HDq3S7CzipbrBHf46NCdu6g4WLtcm5i4jcRvIGiyX+Hfd29jR/30y8uQzIZ2smZC4aVrdeX8bxlacC81NmlnU6gmnUgAxDKM4hGK54LsmRwh6lKfim3SQ2CVwJJCMaLaCn3QfLLWKG09LPGWfYnGr3dzZazCyuTwbZIlblteU4cA036zS3Ng3pbsfjvWpV73ihN9iIf6R33uo6gIkejS8bz1dBlySdkV2Nt27x7RmL5ReRLfDU/PyU7WySE0whrbJ6VZreAeF6yt7bl+ixTnUkh1x/FJFmEfEWH8eCetfezkwmJ704gykKQylEq+/wzMRtDqRtBDZ/6FUlr6pNupXbRbfnAb7 X-OriginatorOrg: foss.st.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2026 08:06:18.0223 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a9dbe4f2-4dc1-4c6a-9925-08decc474f7a X-MS-Exchange-CrossTenant-Id: 75e027c9-20d5-47d5-b82f-77d7cd041e8f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=75e027c9-20d5-47d5-b82f-77d7cd041e8f;Ip=[164.130.1.59];Helo=[smtpO365.st.com] X-MS-Exchange-CrossTenant-AuthSource: DB5PEPF00014B93.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR10MB5998 Hi Guillermo, make sense indeed. Thanks a lot for this patch. On Thu, Jun 11, 2026 at 12:48:56PM +0200, Guillermo Rodríguez wrote: > stm32f7_i2c_compute_timing() derives the I2C clock source period > (i2cclk) with DIV_ROUND_CLOSEST, which may round it up. When the > period is overestimated, all timings computed from it (SCLDEL, > SDADEL, SCLL, SCLH) come out shorter on the wire than calculated, > and the resulting bus rate can exceed the requested speed, violating > the I2C specification minimums for tLOW and tHIGH. > > For example, with a 104.45 MHz clock source (e.g. PCLK1, the > reset-default I2C clock source on STM32MP1), i2cclk is rounded from > 9.574 ns up to 10 ns. Requesting a 400 kHz fast mode bus with > 72/27 ns rise/fall times and no analog/digital filters then produces > an actual bus rate of 415.6 kHz with tLOW = 1254 ns, violating both > the 400 kHz maximum rate and the 1300 ns tLOW minimum of the > specification. > > Truncate the period instead, so that it can only be underestimated. > The error then falls on the safe side: the programmed timings come > out slightly longer than computed and the bus runs marginally below > the target rate (375.3 kHz in the example above) while meeting the > specification. > > i2cbus is left rounded-to-closest: it is only used as the target of > the clk_error comparison and is never multiplied into the programmed > timings, so nearest rounding remains accurate there. > > Fixes: aeb068c57214 ("i2c: i2c-stm32f7: add driver") > Cc: stable@vger.kernel.org > Signed-off-by: Guillermo Rodríguez > --- > drivers/i2c/busses/i2c-stm32f7.c | 9 +++++++-- > 1 file changed, 7 insertions(+), 2 deletions(-) > > diff --git a/drivers/i2c/busses/i2c-stm32f7.c b/drivers/i2c/busses/i2c-stm32f7.c > index 53d9df70ebe4..6439620d6bed 100644 > --- a/drivers/i2c/busses/i2c-stm32f7.c > +++ b/drivers/i2c/busses/i2c-stm32f7.c > @@ -464,8 +464,13 @@ static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev, > { > struct stm32f7_i2c_spec *specs; > u32 p_prev = STM32F7_PRESC_MAX; > - u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC, > - setup->clock_src); > + /* > + * Truncate instead of rounding to closest: if the clock period is > + * overestimated, the computed SCL timings will come out shorter on > + * the wire, which can push the bus above the target rate and below > + * the spec's tLOW/tHIGH minimums. > + */ > + u32 i2cclk = NSEC_PER_SEC / setup->clock_src; > u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC, > setup->speed_freq); > u32 clk_error_prev = i2cbus; > -- > 2.25.1 > Acked-by: Alain Volmat Regards, Alain