From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Cc: "Rodrigo Vivi" <rodrigo.vivi@intel.com>,
"Matthew Brost" <matthew.brost@intel.com>,
"Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
"Raag Jadav" <raag.jadav@intel.com>,
"Michael J . Ruhl" <michael.j.ruhl@intel.com>,
"Mika Westerberg" <mika.westerberg@linux.intel.com>,
"Riana Tauro" <riana.tauro@intel.com>,
"David Airlie" <airlied@gmail.com>,
"Simona Vetter" <simona@ffwll.ch>,
dri-devel@lists.freedesktop.org, intel-xe@lists.freedesktop.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v1 2/2] drm/xe/mcu_i2c: Take over control of the controller enabling
Date: Tue, 23 Jun 2026 13:56:53 +0300 [thread overview]
Message-ID: <ajpmdQjArQkhQ8fl@ashevche-desk.local> (raw)
In-Reply-To: <20260622114759.3464047-3-heikki.krogerus@linux.intel.com>
On Mon, Jun 22, 2026 at 01:47:59PM +0200, Heikki Krogerus wrote:
> Some platforms make an assumption that the i2c controller's
> enabled state indicates also the power state of the
> controller. This can create a problem when the controller is
> in disabled state, because the hardware may assume
> incorrectly that it is then also in low-power state.
>
> To fix this, the controller is kept enabled by taking over
> the IC_ENABLE register. The controller has to be disabled
> when the configuration is updated and when the target
> address or the slave address are assigned, so disabling it
> when IC_CON, IC_TAR or IC_SAR registers are programmed, and
> then re-enabling it again.
...
> +#define IC_CON 0x00
> +#define IC_TAR 0x04
> +#define IC_SAR 0x08
> +#define IC_ENABLE 0x6c
> +#define IC_ENABLE_STATUS 0x9c
Heh, I would like to have a shared header with the registers, but dunno
if the prons will weight out the cons.
...
> +/* See "Disabling DW_apb_i2c" in the DesignWare DW_abp_i2c databook. */
> +static int xe_i2c_disable(struct xe_i2c *i2c)
> +{
> + int timeout = 100;
> + u32 status;
> +
> + do {
> + /* Disable.*/
> + xe_mmio_rmw32(i2c->mmio, XE_REG(IC_ENABLE + I2C_MEM_SPACE_OFFSET), 1, 0);
> +
> + /* Verify. */
> + status = xe_mmio_read32(i2c->mmio, XE_REG(IC_ENABLE_STATUS + I2C_MEM_SPACE_OFFSET));
> + if (!(status & 1))
> + return 0;
> +
> + /* Repeat. */
> + usleep_range(25, 250);
fsleep().
> + } while (timeout--);
> +
> + return -ETIMEDOUT;
> +}
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2026-06-23 10:56 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-22 11:47 [PATCH v1 0/2] drm/xe/i2c: alerts and controller enabling modifications Heikki Krogerus
2026-06-22 11:47 ` [PATCH v1 1/2] drm/xe/i2c: Handler for SMBus Alerts Heikki Krogerus
2026-06-23 10:54 ` Andy Shevchenko
2026-06-23 11:44 ` Heikki Krogerus
2026-06-23 14:34 ` Raag Jadav
2026-06-24 9:23 ` Heikki Krogerus
2026-06-22 11:47 ` [PATCH v1 2/2] drm/xe/mcu_i2c: Take over control of the controller enabling Heikki Krogerus
2026-06-23 10:56 ` Andy Shevchenko [this message]
2026-06-23 14:58 ` Raag Jadav
2026-06-23 18:10 ` Andy Shevchenko
2026-06-24 9:27 ` Heikki Krogerus
2026-06-23 14:39 ` Raag Jadav
2026-06-24 10:13 ` Heikki Krogerus
2026-06-24 11:14 ` Raag Jadav
2026-06-24 11:28 ` Heikki Krogerus
2026-06-23 10:15 ` [PATCH v1 0/2] drm/xe/i2c: alerts and controller enabling modifications Heikki Krogerus
2026-06-23 14:40 ` Raag Jadav
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