From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 799D739184B for ; Tue, 23 Jun 2026 18:10:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782238216; cv=none; b=Tnem6XVc7YCDhxUS67AVgA2bpB7EAfDNuzYqgld/SDcmVrppZAIGViw0GWrTekWdZuUDCzdNjxpZbyP12oV6/OilkNp/8VHpeoQDHYrbKyAtvmHfxy90o15BoLz1L9qWczaTO9MqABg6mdynDb33UUmyFHrLu0Dx1jqKfnWw4Ks= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782238216; c=relaxed/simple; bh=HdcZ4UxFv4lma4c30QOnVADv5AllBw6dqoVSKRKWQ9A=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=SSe+wDw2FEZe9nDbq7PI2knCvvpMp18DsI52Xy02fmvUuQ4afvwqnu5Kpy4Qbdz4e1tnTlWOzmSJvO+UXMuJd5GyuqH+HioSXsNP4xWp2FCwhdeVIe4ZPvUZo0SNEvGC2Xmjfa0ByHfhy6f/XvQVc67h7dxASa+VyDzfNLuAke4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=lpt2Gg4Y; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="lpt2Gg4Y" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1782238213; x=1813774213; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=HdcZ4UxFv4lma4c30QOnVADv5AllBw6dqoVSKRKWQ9A=; b=lpt2Gg4Yr/l4ZXoiwebiUNnwJzm3+DzNMQYVDusWGqECk8emGz9s6YWv z51TDaNEahviBT22F0xp9b54HaKme5xgBx0FmGhyJQ8fSh4AWZ0Nwpzdw x0uivENbKiIzSELfj6IntnFn50LQ9RWS/2gwX5KGK2Nj6N4SqzbPGho1N Y+1uofeTxG8dJvlGRUk+FVpQDXrlw2LkEoCbjl4fuS/7hS8s6KVKMaR7F 4o1oq3v7WRt6b8JinBjmmlINVbmm+7tjPzxsjJYdqcKagmovoMJ4d70mC fS7sTwlnYWfjLX7plv4MxyujuAsbp28qtOQabCbdggMPnxzqmJbMzl54b Q==; X-CSE-ConnectionGUID: fIpGEozpSXG8TAguWG7+nA== X-CSE-MsgGUID: uRbp4/sDQDKnYhC8AYbp8A== X-IronPort-AV: E=McAfee;i="6800,10657,11826"; a="86828399" X-IronPort-AV: E=Sophos;i="6.24,221,1774335600"; d="scan'208";a="86828399" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2026 11:10:13 -0700 X-CSE-ConnectionGUID: 1z3lX5exRQe9p5/awCFuVw== X-CSE-MsgGUID: X24uG0eJTPCluVdZdOhI8Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,221,1774335600"; d="scan'208";a="243222741" Received: from klitkey1-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.244.7]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2026 11:10:10 -0700 Date: Tue, 23 Jun 2026 21:10:07 +0300 From: Andy Shevchenko To: Raag Jadav Cc: Heikki Krogerus , Rodrigo Vivi , Matthew Brost , Thomas =?iso-8859-1?Q?Hellstr=F6m?= , "Michael J . Ruhl" , Mika Westerberg , Riana Tauro , David Airlie , Simona Vetter , dri-devel@lists.freedesktop.org, intel-xe@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v1 2/2] drm/xe/mcu_i2c: Take over control of the controller enabling Message-ID: References: <20260622114759.3464047-1-heikki.krogerus@linux.intel.com> <20260622114759.3464047-3-heikki.krogerus@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo On Tue, Jun 23, 2026 at 04:58:39PM +0200, Raag Jadav wrote: > On Tue, Jun 23, 2026 at 01:56:53PM +0300, Andy Shevchenko wrote: > > On Mon, Jun 22, 2026 at 01:47:59PM +0200, Heikki Krogerus wrote: ... > > > +#define IC_CON 0x00 > > > +#define IC_TAR 0x04 > > > +#define IC_SAR 0x08 > > > +#define IC_ENABLE 0x6c > > > +#define IC_ENABLE_STATUS 0x9c > > > > Heh, I would like to have a shared header with the registers, but dunno > > if the prons will weight out the cons. > > Perhaps something like i2c-algo-pca.h? It's different. It's more device specific header and it doesn't look like a platform data. For SPI PXA2xx we have them in pxa2xx_ssp.h. And we have some device specific i2c headers, seems like the pattern is *_i2c.h, exempli gratia, designware_i2c.h. -- With Best Regards, Andy Shevchenko