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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-30c6eabb7a5sm363369eec.26.2026.06.23.19.43.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jun 2026 19:43:05 -0700 (PDT) Date: Wed, 24 Jun 2026 10:42:58 +0800 From: Shawn Guo To: Taniya Das Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Konrad Dybcio , Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH 4/6] clk: qcom: Add Nord display clock controller support Message-ID: References: <20260623-nords_mm_v1-v1-0-860c84539804@oss.qualcomm.com> <20260623-nords_mm_v1-v1-4-860c84539804@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260623-nords_mm_v1-v1-4-860c84539804@oss.qualcomm.com> X-Proofpoint-ORIG-GUID: -B_TlHeaCZF3cLZQ6FLDDhwNnndax2O3 X-Proofpoint-GUID: -B_TlHeaCZF3cLZQ6FLDDhwNnndax2O3 X-Authority-Analysis: v=2.4 cv=QJhYgALL c=1 sm=1 tr=0 ts=6a3b443a cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=kj9zAlcOel0A:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=uRAUcPz_pJdlg0Cm8TEA:9 a=CjuIK1q_8ugA:10 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNjI0MDAyMSBTYWx0ZWRfX7KoCazpvFHmX r3z1WK0ZGDO2ktxURfV+0XznhhqX2cqpTL8Jb/IGlp0Re4VBV63MO9h4l5OKBukRP8OZJFOm3wo mn8bljkscUEOHXs+QRRNMnu3Jtxu098= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjI0MDAyMSBTYWx0ZWRfXwKlhig4fCQO4 HGL9eVzGCj0riueIHsmVD/Doq4qSZkTBd0/8wZSz90iUnHFnFgqCIzmFWctwr2IxVcP8pZRlOh5 ItgEp21ezGEt4PovRJ9Gh0IzcpzZGOnSwsAQshvbvOsySafNKDh3+oflPNJ0nsse8xS9ezprWWU qN4EX/n3dgZ5yMzBnhcLux5+BcepaZ+/8xdkkOo8yLCB4RdWj0f7B+9lqRYaIjSCVceBLW8LwW0 VeFCXwqfpf2qcZS7NLnV39EyZEbU21ywhX86Tp08UyjftDsQVc9/heA1f+iDHuhAH+t88Er0PJt +oG0g991n/PcSuTLuoFcjIQqW2ZX4l0PRzLTbtwwOkdvAWdIutISUeBjmQbZEdSP5PusDrlkpOV nlLHSy9fwk3LYw0yXU6Hscyv8oEmnayupEtvQiLDUmTe0tqiQelaucFVZvl+zwAsE8IFBZajyta pydapJzPoVw+gck0i7A== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-24_01,2026-06-23_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 bulkscore=0 adultscore=0 suspectscore=0 lowpriorityscore=0 phishscore=0 malwarescore=0 priorityscore=1501 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606240021 On Tue, Jun 23, 2026 at 04:24:07PM +0530, Taniya Das wrote: > Add support for the display clock controllers (DISPCC) on the > Qualcomm Nord platform. > > The platform includes two display clock controller instances, > display0 and display1. Register support for both controllers. > > Signed-off-by: Taniya Das > --- > drivers/clk/qcom/Kconfig | 11 + > drivers/clk/qcom/Makefile | 1 + > drivers/clk/qcom/dispcc0-nord.c | 2006 +++++++++++++++++++++++++++++++++++++++ > drivers/clk/qcom/dispcc1-nord.c | 2006 +++++++++++++++++++++++++++++++++++++++ > 4 files changed, 4024 insertions(+) > > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig > index 7d84c2f1d911a35430bba7670409f59972dcca0f..874136a2ad9aaa117df2c7ad5c8abc5280b76339 100644 > --- a/drivers/clk/qcom/Kconfig > +++ b/drivers/clk/qcom/Kconfig > @@ -145,6 +145,17 @@ config CLK_KAANAPALI_VIDEOCC > Say Y if you want to support video devices and functionality such as > video encode/decode. > > +config CLK_NORD_DISPCC > + tristate "Nord Display Clock Controller" > + depends on ARM64 || COMPILE_TEST > + select CLK_NORD_GCC > + default m if ARCH_QCOM > + help > + Support for the display clock controllers on Qualcomm Technologies, Inc > + Nord devices. There are two display clock controllers on Nord SoC. > + Say Y if you want to support display devices and functionality such as > + splash screen. > + > config CLK_NORD_GCC > tristate "Nord Global Clock Controller" > depends on ARM64 || COMPILE_TEST > diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile > index 58f9a5eb6fd7fc457607a179d8bab5623fedf706..4282f43e7078f1fe0dde6f942040eb6bd122d7ce 100644 > --- a/drivers/clk/qcom/Makefile > +++ b/drivers/clk/qcom/Makefile > @@ -37,6 +37,7 @@ obj-$(CONFIG_CLK_KAANAPALI_GCC) += gcc-kaanapali.o > obj-$(CONFIG_CLK_KAANAPALI_GPUCC) += gpucc-kaanapali.o gxclkctl-kaanapali.o > obj-$(CONFIG_CLK_KAANAPALI_TCSRCC) += tcsrcc-kaanapali.o > obj-$(CONFIG_CLK_KAANAPALI_VIDEOCC) += videocc-kaanapali.o > +obj-$(CONFIG_CLK_NORD_DISPCC) += dispcc0-nord.o dispcc1-nord.o > obj-$(CONFIG_CLK_NORD_GCC) += gcc-nord.o negcc-nord.o nwgcc-nord.o segcc-nord.o > obj-$(CONFIG_CLK_NORD_TCSRCC) += tcsrcc-nord.o > obj-$(CONFIG_CLK_X1E80100_CAMCC) += camcc-x1e80100.o > diff --git a/drivers/clk/qcom/dispcc0-nord.c b/drivers/clk/qcom/dispcc0-nord.c > new file mode 100644 > index 0000000000000000000000000000000000000000..c0097482a1a94a99a05767726b5a7405cf014fea > --- /dev/null > +++ b/drivers/clk/qcom/dispcc0-nord.c > @@ -0,0 +1,2006 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. > + */ > + > +#include > +#include > +#include > +#include This include shouldn't be needed. Shawn > +#include > +#include