From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 614963A6F16 for ; Wed, 24 Jun 2026 09:27:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782293249; cv=none; b=ldWwv1+fF3CoXYvGaI3ZJq56h9nbCZgzmuhAVdBCBasLt3+B6mWD508M5HmE26i6uqY6r+VCXJDi1nRnRnFvK1G3LOYUMnJvy+FtfacLiwc6o2qpWaAHm2I/GzDebk7DqieU4BXqsjXFyuhucWE5eViQV4zRCQgtGnLFmNCD7NQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782293249; c=relaxed/simple; bh=dI0O288id5nByduVA0CM6QTnd06XGS0SpN64DxnqARQ=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=aQzIOi62nqF1Q1lMsT7aF9qIAZGHUmKbx8ZfEAp+DSt/3fCqtzH9dBluvWQPQSiDqPWi0vUEyoYpV6QghDiI6eOG6VJQlZQVEythGQk61CmVwd3MI863cpVezneKVuw6f4NQNuMaZ9fHL7EBcDDtBK4+LCDBoYT8oNVWCPQ4gr0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=VhxkMXxm; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="VhxkMXxm" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1782293236; x=1813829236; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=dI0O288id5nByduVA0CM6QTnd06XGS0SpN64DxnqARQ=; b=VhxkMXxmbm5mi6HJHQ17F33ykbjP83LN7oCkpRB7bVD7Fi1qoN90H4bo x7z+rG4aox0rvp5ChewXFc3vbaB4vpQNSWtOd1RNwWfc4H0L+QxlhE6MR rCys32dkN6dT4685+GPLxXvwuzMfnryWR1TvYNce1kydOr9NjCahYBKt4 Nques4dsdsYr8B3TNIm4ba2MKmJn5ceX4ihqz42tqee0NK5GUX7WKwcTV 4LUs5hrhZwiQfbTZrnRn2CfwK3CRE/PtMRQguHlIPTvxcfC+I0Of5RGWS QQXnv/wKl+GEKRLa/xq6xbIrjYKhMgU7r1fboMoxAhV8lWxpZ0OFQWLBy A==; X-CSE-ConnectionGUID: lLNgiWbgSJKywuL3Lbg0uQ== X-CSE-MsgGUID: djhgyqfSRYqWoRRpf8Wmdg== X-IronPort-AV: E=McAfee;i="6800,10657,11826"; a="86731953" X-IronPort-AV: E=Sophos;i="6.24,222,1774335600"; d="scan'208";a="86731953" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2026 02:27:15 -0700 X-CSE-ConnectionGUID: XdfY8CY0SduRc8eSn4RE8w== X-CSE-MsgGUID: hF6WLbKETgOnCpRIH38j7A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,222,1774335600"; d="scan'208";a="273854445" Received: from black.igk.intel.com ([10.91.253.5]) by fmviesa001.fm.intel.com with ESMTP; 24 Jun 2026 02:27:12 -0700 Received: by black.igk.intel.com (Postfix, from userid 1008) id 1DADD95; Wed, 24 Jun 2026 11:27:12 +0200 (CEST) Date: Wed, 24 Jun 2026 12:27:10 +0300 From: Heikki Krogerus To: Andy Shevchenko Cc: Raag Jadav , Rodrigo Vivi , Matthew Brost , Thomas =?iso-8859-1?Q?Hellstr=F6m?= , "Michael J . Ruhl" , Mika Westerberg , Riana Tauro , David Airlie , Simona Vetter , dri-devel@lists.freedesktop.org, intel-xe@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v1 2/2] drm/xe/mcu_i2c: Take over control of the controller enabling Message-ID: References: <20260622114759.3464047-1-heikki.krogerus@linux.intel.com> <20260622114759.3464047-3-heikki.krogerus@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Tue, Jun 23, 2026 at 09:10:07PM +0300, Andy Shevchenko wrote: > On Tue, Jun 23, 2026 at 04:58:39PM +0200, Raag Jadav wrote: > > On Tue, Jun 23, 2026 at 01:56:53PM +0300, Andy Shevchenko wrote: > > > On Mon, Jun 22, 2026 at 01:47:59PM +0200, Heikki Krogerus wrote: > > ... > > > > > +#define IC_CON 0x00 > > > > +#define IC_TAR 0x04 > > > > +#define IC_SAR 0x08 > > > > +#define IC_ENABLE 0x6c > > > > +#define IC_ENABLE_STATUS 0x9c > > > > > > Heh, I would like to have a shared header with the registers, but dunno > > > if the prons will weight out the cons. > > > > Perhaps something like i2c-algo-pca.h? > > It's different. It's more device specific header and it doesn't look like > a platform data. For SPI PXA2xx we have them in pxa2xx_ssp.h. And we have > some device specific i2c headers, seems like the pattern is > *_i2c.h, exempli gratia, designware_i2c.h. Okay, I'll add a patch the series where I'll move the register definitions to include/linux/designware_i2c.h Cheers, -- heikki