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Tue, 30 Jun 2026 08:04:40 -0700 (PDT) Date: Tue, 30 Jun 2026 16:04:38 +0100 From: William Bright To: Konrad Dybcio Cc: Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: Re: [PATCH v4 4/4] arm64: dts: qcom: Add IMDT QCS8550 SBC Message-ID: References: <20260610-imdt-qcs8550-sbc-rfc-v4-0-358e71d606bc@imd-tec.com> <20260610-imdt-qcs8550-sbc-rfc-v4-4-358e71d606bc@imd-tec.com> <8afbc9f9-15ff-4b60-9a0f-845f903d3c9a@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Mon, Jun 29, 2026 at 04:03:18PM +0200, Konrad Dybcio wrote: > On 6/29/26 12:25 PM, William Bright wrote: > > On Fri, Jun 26, 2026 at 05:18:20PM +0200, Konrad Dybcio wrote: > > [...] > > > The PCIe switch we are using is a NXP CBTU02044HEJ, this is a simple > > 1->2 switch that is not PCIe enumerable. Given that there isn't support > > for this IC already in the kernel and that it will take quite a few > > weeks/months for me to cobble something together, I am thinking that it > > might make sense to drop PCIe support from this patch-series in V5 and > > then submit a seperate patch-series with a driver and bindings for this > > IC whenever I get something working. Are you OK with this? > > Sure > > I'm a bit curious why do you have a switch there in the first > place - is there anything else connected to the other port? > Yeah both PCIe ports are used. Here's a diagram of both pcie0 and pcie1: pcie0 pcie1 | | | | | | | | | v | +-------------------+ | | PCIe Switch | | | CBTU02044HEJ | | +-------------------+ | / \ | / \ | / GPIO16 = Low \ GPIO16 = High v v v +-------------------+ +-----------+ +-------------+ | M.2 Key E | | LAN7430 | | M.2 Key B | | Slot | | (Gigabit | | Slot | | | | Ethernet) | | | +-------------------+ +-----------+ +-------------+ We used the CBTU02044HEJ PCIe switch on pcie1 so that we could use pcie1 for ethernet or M.2 Key B with static boot-time selection of either. My limited understanding is that enumerable PCIe switches are expensive and hard to get although that might be changing. With pcie0 it looks like I can just add the Key E connector DT node like you suggested and I will drop pcie1 support for now. > Would you like for that to be switchable at runtime? > > +Mani will probably be interested > > Konrad I didn't intend for this to be possible but its not a negative if this can be done. My original plan was to use the below .dtso when using Key B: // SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2026 IMD Technologies Ltd * * There are two options for PCIe routing on the IMDT QCS8550 SBC. * By default, the PCIe switch is configured to route to the GBE PHY, but * this can be changed to route to the M.2 slot Key B by setting * pcie_switch_sel_gpio high */ /dts-v1/; /plugin/; #include &pcie_switch_sel_gpio { /* Change the PCIe switch so that key B routing is selected by * inverting the GPIO polarity. */ gpios = <16 GPIO_ACTIVE_LOW>; }; Regards Will