From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4B24F2D839C for ; Thu, 2 Jul 2026 10:47:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782989231; cv=none; b=XCd5i2DKX05wei06ORa+kd4R7ZaO9eGJxKBYxbOwPkvZTWk8+IqCziV39Wu2L8glsgmzSGBCNv1+k6DyOoHdo+awfcmVzgsi9f7s3iq6gbuAMDYldrhzGyzIPsIY9cDQxXb6VOlvwy7nkq48T0gnPdq0VMxePF8OG8wgpYb3w7c= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782989231; c=relaxed/simple; bh=oJKoNavg0JVxJbLt0HN3PVf8W61ExetBHTFOSEEZlXc=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=qy6i62W9PSvGvh4Y6+Iz9fMHX8a4+6AbZGzMReMH61+Gt012icqsK6+L+89gfpw9szDXAXZbz9hNwoUIWqI13ul2FbEEmIO9ILtYktjdftbfRidOmrb6eXtJJrGw9kSOPQBn6J93/00sF4a0i/3bmD3DTjuTx7uaj92voUXzQ28= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=Nxizj05O; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="Nxizj05O" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E17FD359D; Thu, 2 Jul 2026 03:47:03 -0700 (PDT) Received: from J2N7QTR9R3 (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id AFCC73F905; Thu, 2 Jul 2026 03:47:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1782989228; bh=oJKoNavg0JVxJbLt0HN3PVf8W61ExetBHTFOSEEZlXc=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=Nxizj05OzNCOPrF2vDD88XV9HOhYmOfF/UqKyxsu6cO7/1Co/EgfZ6Fec/O5w8Lte nf3fvE8IclU+bHqBfQTEhtDhiIXRHw6KK6AKx10lMTGL8DY3+u8uoAeHvile4DsczI tlzunPwRlGlxRe5zWeiQw6QjWAIrdhAEddjZY/rY= Date: Thu, 2 Jul 2026 11:47:04 +0100 From: Mark Rutland To: Linu Cherian Cc: Catalin Marinas , Will Deacon , Ryan Roberts , Kevin Brodsky , Anshuman Khandual , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 5/5] arm64: cpufeature: Extend bbml3 support list Message-ID: References: <20260701094131.677636-1-linu.cherian@arm.com> <20260701094131.677636-6-linu.cherian@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260701094131.677636-6-linu.cherian@arm.com> On Wed, Jul 01, 2026 at 03:11:31PM +0530, Linu Cherian wrote: > Add below cpus to the midr list, which supports > BBML3 but don't advertise through MMFR2 ID. > > Cortex A520(AE) > Cortex A715 > Cortex A720(AE) > Cortex A725 > Neoverse N3 > C1-Nano > C1-Pro > C1-Ultra > C1-Premium > > Signed-off-by: Linu Cherian > --- > arch/arm64/kernel/cpufeature.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index d754b1b7da77..9b806c1c60aa 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -2142,6 +2142,15 @@ bool cpu_supports_bbml3(void) > MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS), > MIDR_ALL_VERSIONS(MIDR_AMPERE1), > MIDR_ALL_VERSIONS(MIDR_AMPERE1A), > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A520AE), > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A715), > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A720AE), > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A725), > + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N3), > + MIDR_ALL_VERSIONS(MIDR_C1_NANO), > + MIDR_ALL_VERSIONS(MIDR_C1_PRO), > + MIDR_REV_RANGE(MIDR_C1_ULTRA, 1, 1, 0xf), > + MIDR_REV_RANGE(MIDR_C1_PREMIUM, 1, 1, 0xf), Why do these two have a range? The commit message didn't mention this. Mark.