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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-30f0b816a42sm76309105eec.9.2026.07.05.20.28.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Jul 2026 20:28:35 -0700 (PDT) Date: Sun, 5 Jul 2026 20:28:33 -0700 From: Qiang Yu To: Konrad Dybcio Cc: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 0/3] phy: qcom: qmp-pcie: Add vdda-refgen supply support for Glymur Message-ID: References: <20260623-phy_refgen-v2-0-4d15983bf91d@oss.qualcomm.com> <8811c181-9caf-4797-8e17-52311702e292@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-Proofpoint-Spam-Info: AW1haW4tMjYwNzA2MDAzMSBTYWx0ZWRfX3A1fns0/FYOu 3HKNx4CGDW5hBQjWmJbwYkIkO6CwCNBeN/Bsz6rQYN3vu/08cyUCh93UVZcDS1wIcaPfDaHVbX0 8LHlL1bWOsCzZWZ3GR+I5tLufO6xRvU= X-Proofpoint-ORIG-GUID: 2khpJ5qWAFWich7WVzRaRsJc-2OkRl1e X-Authority-Analysis: v=2.4 cv=J+yaKgnS c=1 sm=1 tr=0 ts=6a4b20e5 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=mkIokxEfF-L8pB4xSJ8A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzA2MDAzMSBTYWx0ZWRfX8l9/yaEkAGn3 vjrLaoTyjJHSIgvykGsDvvp/f4Ek85lzJSc3FHRBfx5MrUowmvmuwD+lWxvGFjGwRjbRcx3zTXh nsOwegSZS3ldlnBY3r9W0XqcHUSmBUzGpNBHoK6nhSrtlym5Jsj5jtGAlloA9+NPSpFO+993xmN 9mZ8c8dCfuV4Iik+9uQcnapfR6lnjrf2Z6RELmLD7pCzxLabUnW/erxXuHONCn/4f8KANHAgsK+ Cf96oOCc8U6o2ie+rXAaaM0indU4XJYnZm8+2dj4dVFrYbFQgF6eOP/di+fnZRDVXhe6bNT9Jov Nc7mPUpCWT76kEatzy6F4Xo7BaL+vNqIMOTfk0Deb6Af68ymPag5xPrXKtD/0Z0+vgV90trklJV YiUpNscVnITRsCcciIKERxMLFiaHZr6Sro+zkTjJzVu9NHxQScT4t8AMSfGAljlrJpeNNDE5OuV wXH/2bqBphYM1R67PAg== X-Proofpoint-GUID: 2khpJ5qWAFWich7WVzRaRsJc-2OkRl1e X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-07-05_02,2026-07-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 spamscore=0 priorityscore=1501 phishscore=0 impostorscore=0 adultscore=0 clxscore=1015 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607060031 On Mon, Jun 29, 2026 at 02:18:35PM +0200, Konrad Dybcio wrote: > On 6/29/26 2:14 PM, Qiang Yu wrote: > > On Mon, Jun 29, 2026 at 12:51:55PM +0200, Konrad Dybcio wrote: > >> On 6/23/26 3:05 PM, Qiang Yu wrote: > >>> The PCIe QMP PHYs on Glymur require both refgen for stable reference > >>> voltage and qref for stable reference clock. The refgen requires two power > >>> supplies: vdda-refgen0p9 and vdda-refgen1p2. > >>> > >>> can be extended in the future. > >>> > >>> This series creates a Glymur-specific supply list including the refgen > >>> supplies and updates both Gen5x4 and Gen4x2 configurations to use it. > >>> > >>> Signed-off-by: Qiang Yu > >>> > >>> Changes in v2: > >>> - Add dts patch in this series. > >>> - Reword commit msg of dtbinding patch. > >>> - Link to v1: https://lore.kernel.org/all/20260208-refgen-v1-0-87ca84fd78b3@oss.qualcomm.com/ > >>> > >>> --- > >> > >> Is this necessary (for Glymur) now that we correlated some of the > >> TCSR clocks with the right nodes? > > > > This patch is necessary for glymur and mahua and other Qualcomm targets, > > which can be verified from the REFGEN page and power grid page on ipcat. > > > > Take Glymur PCIe3 PHY as an example: it requires two REFGENs — REFGEN0 for > > the PHY itself and REFGEN4 for QREF. In the TCSR driver, only the LDOs for > > REFGEN4 are voted, not REFGEN0. This is intentional: each consumer is > > responsible for voting the LDOs of the REFGEN it uses. Since QREF uses > > REFGEN4, the TCSR driver votes the REFGEN4 LDOs; since the PHY uses > > REFGEN0, the PHY driver votes the REFGEN0 LDOs. > > > > For some PHY instances in power grid, you can only see one REFGEN, that > > indicates the phy doesn't require QREF or the phy and the QREF it requires > > share same REFGEN. > >> > >> Perhaps this would be necessary for Mahua since its clocks don't > >> require QREF (or we can lie about it and handle them there)? > > > > For Mahua PCIe5 PHY, it doesn't require QREF. So we don't need to vote > > REFGEN LDOs for QREF in tcsr driver. But the PHY requires REFGEN. So we > > still need to vote in PHY driver. > > OK, I think I got my mental model of all of this straight. But expect > me to make more mistakes and sorry for that! No worries at all. Glad the REFGEN and QREF topology is clear now. Thanks for the review. - Qiang Yu