From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADF3C4D8DB3 for ; Tue, 21 Jul 2026 15:11:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784646700; cv=none; b=PqaD3VTjNcFOIEQ5d64fsDQgSvHxK4n5/AY1ONFskClTR9G2ol/MFNbyiA/Sn73XIu1RA2j+eKrMROzhYN1kV3o+JIRYzBPCc/S6CWG5IMtyL81TynUbiUWcJIe7J0IOrgj0VKlWDsUD0PPrmqifR/BF3t8ZMwB6FebAEIxeV8o= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784646700; c=relaxed/simple; bh=5N194Aozb7lZW74BDVkII94LiXpnW9Qz4D9cU43ZdfI=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=SyJ7FQ6iV31fBJlkd5cD5NdHK+WHWDgOuIy69PTRMo2ca7EIdv4CKQ8sWw9AiN9nFicTF5NWQAXGOgIoXRdr0SYNSRLnjR2JqyIDfUU7a8UzCONu1qZfIjJJtWB1JkbWoq7Nmsc9k6PLUTQvpBLMd1NNvpdvFZuC6osLH+08ZO0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=R9OWAVTE; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="R9OWAVTE" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3EAD81F00A3D; Tue, 21 Jul 2026 15:11:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784646697; bh=FYnEpm9v0G/lVuR4rZTj+1KLTE5h9epDTFOEUQYssKQ=; h=Date:From:To:Cc:Subject:References:In-Reply-To; b=R9OWAVTEG/M5V6quVfi/FKXThTlKlY62+FNTYYt20lnbuHnyaXpb3q/lg7SlA7UaD S2qSPH9XDCc6F2VdXyBe5BaW+oicsrdUWaYb81ZEl5nn6XP2Q+OCDBki/Jt7PKKzRa vOl9Aqk6TyWmc8UMNEPhWm7ow/AFRjWnDxnu3qOaqrnWfjGPH70rFt0nC2SGlOoy1L g+uv2O7WRIyabEIe9LmhJn5ZjDIAsXCibayBe/CUFWujvQDUXWRDDCet7vI3sioPWs e92Zf8NJ29bwYUq+gu4zO+cngMhEPRJqUMRRADo9lZPQeY22Ny2QUYfgqetK0VtDLH WAtpgR2/jV1Qw== Date: Tue, 21 Jul 2026 09:11:32 -0600 From: Keith Busch To: Fengnan Chang Cc: hch@lst.de, andriy.shevchenko@intel.com, axboe@kernel.dk, gang.cao@intel.com, jun.i.jin@intel.com, jun1.zeng@intel.com, liang.a.fang@intel.com, linux-kernel@vger.kernel.org, linux-nvme@lists.infradead.org, sagi@grimberg.me, tglx@kernel.org, yong.hu@intel.com, guzebing@bytedance.com Subject: Re: [PATCH v1 1/1] nvme-pci: adaptive interrupt coalescing Message-ID: References: <20260715075703.15578-1-jun1.zeng@intel.com> <20260715075703.15578-2-jun1.zeng@intel.com> <20260720150539.GB17986@lst.de> <20260721083739.69676-1-changfengnan@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260721083739.69676-1-changfengnan@bytedance.com> On Tue, Jul 21, 2026 at 04:37:39PM +0800, Fengnan Chang wrote: > @@ -1618,6 +1748,8 @@ static inline bool nvme_poll_cq(struct nvme_queue *nvmeq, > * the cqe requires a full read memory barrier > */ > dma_rmb(); > + if (sq_head) > + *sq_head = le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].sq_head); This is the wrong criteria to determine the outstanding depth. The spec allows the controller to move this forward after it has read an entry. The commands may still be in progress, so the depth of future completions to expect can't depend on this value. But in general, I agree with the spirit of where this is going. For MSI, you can make use of the INTMS/INTMC NVMe registers to make this even more efficient. Your patch disables the irq at the cpU level, but the device is still emitting those messages for no reason.