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AHgh+RpUT8Mmv8K4DCJSVLkm63/RoBpg/1AvQCxmn5A8W+c91FzQ8yVYfvYR0LVzs/FfQPGSttEFGzx+z39MidU=@vger.kernel.org X-Gm-Message-State: AOJu0YzIw5i3c4Hkwt1KwXBAx5mHBFTweg8+HsCY9AZ0Xp4g3h0QxjI8 +LVA2XSozGy1P/i+05ksGJ1ClsZL8LL9U0PShkxlpYf/E0YyurdWWr9dFThnKuVNkUl7unluLMH klQVkyA== X-Received: from pjdn90.prod.google.com ([2002:a17:90a:2ce3:b0:37f:acb7:9d81]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90a:d60f:b0:37e:b6a:6cdf with SMTP id 98e67ed59e1d1-38e4b538979mr19429131a91.20.1784653516620; Tue, 21 Jul 2026 10:05:16 -0700 (PDT) Date: Tue, 21 Jul 2026 10:05:16 -0700 In-Reply-To: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260720192221.72912-1-absandze@amazon.de> Message-ID: Subject: Re: [RFC PATCH 0/2] KVM: x86/pmu: Let userspace disable SW accounting of emulated instructions From: Sean Christopherson To: David Woodhouse Cc: Luka Absandze , Paolo Bonzini , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Alexander Graf Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable On Tue, Jul 21, 2026, David Woodhouse wrote: > On Tue, 2026-07-21 at 09:47 -0700, Sean Christopherson wrote: > > On Tue, Jul 21, 2026, David Woodhouse wrote: > > > On Mon, 2026-07-20 at 19:22 +0000, Luka Absandze wrote: > > > > On hosts that run guests with an *emulated* vPMU -- guest PMU MSR > > > > accesses trap into KVM and each guest counter is backed by a host > > > > perf_event -- the per-emulated-instruction PMU accounting added by = commit > > > > 9cd803d496e7 ("KVM: x86: Update vPMCs when retiring instructions") = is > > > > pathologically expensive. > > >=20 > > > Given that the guest PMU MSR accesses are trapped... is there a reaso= n > > > we can't fold a *separate* count of emulated instructions into the > > > value we return to the guest? > > >=20 > > > I guess the overflow would come late... but isn't that tolerable?=20 > >=20 > > Like ignoring emulated instructions entirely, it probably depends on th= e guest. > >=20 > > > And we could probably impose a limit on how large the addend could be= =E2=80=94 even > > > if we only reprogram the PMU once every 100 times, that's still a win= ? > >=20 > > Hmm, yeah, that'd be better than ignoring emulated instruction entirely= , and > > would give userspace far better control over how shoddy KVM's emulation= is.=C2=A0 Off > > the cuff, the change would be fairly trivial too?=C2=A0 E.g. > >=20 > > diff --git arch/x86/kvm/pmu.c arch/x86/kvm/pmu.c > > index 7f777049d328..c5f436c6f83f 100644 > > --- arch/x86/kvm/pmu.c > > +++ arch/x86/kvm/pmu.c > > @@ -1084,7 +1084,8 @@ static void kvm_pmu_incr_counter(struct kvm_pmc *= pmc) > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 */ > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (!kvm_vcpu_has_mediated_p= mu(vcpu)) { > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 pmc->emulated_counter++; > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 kvm_pmu_request_counter_reprogram(pmc); > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 if (pmc->emulated_counter > pmu_something_something_toleran= ce) > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 kvm_pmu_req= uest_counter_reprogram(pmc); > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 return; > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 } > >=20 >=20 > We also want to add the same delta when the the guest reads the counter? Isn't that already handled by pmc_read_counter()? Or am I misunderstanding= the concern? static inline u64 pmc_read_counter(struct kvm_pmc *pmc) { u64 counter, enabled, running; if (kvm_vcpu_has_mediated_pmu(pmc->vcpu)) return pmc->counter & pmc_bitmask(pmc); counter =3D pmc->counter + pmc->emulated_counter; <=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D if (pmc->perf_event && !pmc->is_paused) counter +=3D perf_event_read_value(pmc->perf_event, &enabled, &running); /* FIXME: Scaling needed? */ return counter & pmc_bitmask(pmc); }