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Sat, 11 Jul 2026 22:45:58 -0700 (PDT) Date: Sun, 12 Jul 2026 13:45:15 +0800 From: Inochi Amaoto To: Andy Shevchenko , Inochi Amaoto Cc: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Christian Bruel , Frank Li , Nam Cao , Qiang Yu , Krishna Chaitanya Chundru , Xincheng Zhang , Alex Elder , Siddharth Vadapalli , Vidya Sagar , Neil Armstrong , Gustavo Pimentel , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, Yixun Lan , Longbin Li Subject: Re: [PATCH v4 6/6] PCI: spacemit-k1: Add Spacemit K3 PCIe host controller support Message-ID: References: <20260709040027.958400-1-inochiama@gmail.com> <20260709040027.958400-7-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Thu, Jul 09, 2026 at 10:21:18AM +0300, Andy Shevchenko wrote: > On Thu, Jul 09, 2026 at 12:00:26PM +0800, Inochi Amaoto wrote: > > The PCIe controller on Spacemit K3 is almost a standard Synopsys > > DesignWare PCIe IP with extra link and reset control. Unlike > > the PCIe controller on K1, this controller supports external MSI > > interrupt controller and can use multiple PHYs at the same time. > > > > Add driver to support PCIe controller on Spacemit K3 PCIe. > > ... > > > + /* K3: Set IGNORE_PERSTN and drive PERSTN_OE high (assert reset) */ > > + regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CONTROL_LOGIC, > > + PCIE_IGNORE_PERSTN | PCIE_PERSTN_OE | PCIE_PERSTN_OUT); > > + usleep_range(1000, 2000); > > fsleep(1 * USEC_PER_MSEC) > > > + regmap_clear_bits(k1->pmu, k1->pmu_off + PCIE_CONTROL_LOGIC, PCIE_PERSTN_OUT); > > + > > + msleep(PCIE_T_PVPERL_MS); > > If PCIE_T_PVPERL_MS is too small, msleep() maybe not a good choice, > perhaps > > fsleep(PCIE_T_PVPERL_MS * USEC_PER_MSEC) > > ... > > > + val = u32_replace_bits(val, BIT(7), > > + GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC); > > It's perfectly a single line. > > ... > > > static const struct of_device_id k1_pcie_of_match_table[] = { > > { .compatible = "spacemit,k1-pcie", .data = &k1_pcie_device_data}, > > + { .compatible = "spacemit,k3-pcie", .data = &k3_pcie_device_data}, > > Missed space. > > > { } > > }; > > I don't see (and haven't checked) the context, do you have > MODULE_DEVICE_TABLE() for this? > IIRC there is already a patch for adding this, so I won't add MODULE_DEVICE_TABLE there. I will take other advice, thanks. > -- > With Best Regards, > Andy Shevchenko > > Regards, Inochi