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[93.144.65.248]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49510c8e220sm45791165e9.15.2026.07.14.00.39.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jul 2026 00:39:31 -0700 (PDT) Date: Tue, 14 Jul 2026 09:39:29 +0200 From: Stefano Radaelli To: Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, pierluigi.p@variscite.com, matthias.p@variscite.com, Stefano Radaelli , Nishanth Menon , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley Subject: Re: [PATCH v2 1/4] arm64: dts: ti: var-som-am62p: fix Ethernet PHY configuration Message-ID: References: <4d1ba0d1b9bd4957224213cf17dca93392788e03.1782680023.git.stefano.r@variscite.com> <531d7396-c581-4b5d-8008-db5e9ee5e7d6@ti.com> <178400918994.3109814.1083731005888044586.b4-reply@b4> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <178400918994.3109814.1083731005888044586.b4-reply@b4> On Tue, Jul 14, 2026 at 11:36:29AM +0530, Vignesh Raghavendra wrote: > On 2026-07-13 15:32:00+02:00, Stefano Radaelli wrote: > > On Mon, Jul 13, 2026 at 04:02:34PM +0530, Vignesh Raghavendra wrote: > > > > > > > > > > > > So are the reset delays no longer required? Or they taken care of > > > somewhere else? > > > > > > > > > > Hi Vignesh, > > > > No, because this GPIO actually is not used as a PHY reset. > > > > After reviewing the hardware, it turned out that this signal is a > > board-level enable signal required for the PHY to operate, rather than > > a reset line. > > The previous reset-assert-us and reset-deassert-us values were > > associated with the incorrect modelling of this GPIO as a reset, and > > are not longer needed. > > > > Along the same lines does [0] need update to how the cpsw3g_phy0 is > described then as its seems very similar to what this patch is addressing? > > [0] https://lore.kernel.org/linux-arm-kernel/0a7bdfda80309eaa207b5b369d72f4bcb16e0604.1783864932.git.stefano.r@variscite.com/ > > > > > Best Regards, > > Stefano > Hi Vignesh, No, the AM62 DTS referenced in [0] does not need the same update. The VAR-SOM-AM62 uses a different Ethernet PHY and has separate signals for the PHY supply enable and PHY reset. In that design, GPIO0_45 controls the PHY 3.3 V supply, while GPIO0_46 is connected to the PHY reset input, so the existing reset-gpios description is correct. The issue addressed by this patch is specific to the VAR-SOM-AM62P. Thank you for your review, Best Regards, Stefano