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From: Klara Modin <klarasmodin@gmail.com>
To: Xu Lu <luxu.kernel@bytedance.com>
Cc: paul.walmsley@sifive.com, palmer@dabbelt.com,
	aou@eecs.berkeley.edu,  alex@ghiti.fr,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	 apw@canonical.com, joe@perches.com
Subject: Re: [PATCH RESEND 1/2] riscv: mm: Apply svinval in update_mmu_cache()
Date: Wed, 15 Jul 2026 03:14:25 +0200	[thread overview]
Message-ID: <albbQtulrnpOmmBp@soda.int.kasm.eu> (raw)
In-Reply-To: <20250901114141.5438-2-luxu.kernel@bytedance.com>

Hi,

On 2025-09-01 19:41:40 +0800, Xu Lu wrote:
> Only flush tlb of the specified mm, and apply svinval if available.
> 
> Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
> ---
>  arch/riscv/include/asm/pgtable.h  | 16 +++++++++++++++-
>  arch/riscv/include/asm/tlbflush.h | 23 +++++++++++++++++++++++
>  arch/riscv/mm/tlbflush.c          | 23 -----------------------
>  3 files changed, 38 insertions(+), 24 deletions(-)
> 
> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> index 91697fbf1f901..165cd02d51629 100644
> --- a/arch/riscv/include/asm/pgtable.h
> +++ b/arch/riscv/include/asm/pgtable.h
> @@ -495,9 +495,15 @@ static inline void update_mmu_cache_range(struct vm_fault *vmf,
>  		struct vm_area_struct *vma, unsigned long address,
>  		pte_t *ptep, unsigned int nr)
>  {
> +	int i;
> +	unsigned long asid = get_mm_asid(vma->vm_mm);
> +
>  	asm goto(ALTERNATIVE("nop", "j %l[svvptc]", 0, RISCV_ISA_EXT_SVVPTC, 1)
>  		 : : : : svvptc);
>  
> +	asm goto(ALTERNATIVE("nop", "j %l[svinval]", 0, RISCV_ISA_EXT_SVINVAL, 1)
> +		 : : : : svinval);
> +
>  	/*
>  	 * The kernel assumes that TLBs don't cache invalid entries, but
>  	 * in RISC-V, SFENCE.VMA specifies an ordering constraint, not a
> @@ -506,7 +512,15 @@ static inline void update_mmu_cache_range(struct vm_fault *vmf,
>  	 * the extra traps reduce performance.  So, eagerly SFENCE.VMA.
>  	 */
>  	while (nr--)
> -		local_flush_tlb_page(address + nr * PAGE_SIZE);
> +		local_flush_tlb_page_asid(address + nr * PAGE_SIZE, asid);
> +	return;
> +
> +svinval:
> +	local_sfence_w_inval();

> +	for (i = 0; i < nr; i++)
> +		local_sinval_vma(address + nr * PAGE_SIZE, asid);

Probably should be

 +	for (i = 0; i < nr; i++)
 +		local_sinval_vma(address + i * PAGE_SIZE, asid);

instead. My BPI-f3 hangs when entering the initramfs with the original
patch. Reverting also fixes it.

> +	local_sfence_inval_ir();
> +	return;
>  
>  svvptc:;
>  	/*

Regards,
Klara Modin

...

  parent reply	other threads:[~2026-07-15  1:14 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-01 11:41 [PATCH RESEND 0/2] riscv: mm: Some optimizations for tlb flush Xu Lu
2025-09-01 11:41 ` [PATCH RESEND 1/2] riscv: mm: Apply svinval in update_mmu_cache() Xu Lu
2026-07-11  0:04   ` Paul Walmsley
2026-07-13  6:29     ` [External] " Xu Lu
2026-07-13 17:49       ` Paul Walmsley
2026-07-11  0:07   ` Paul Walmsley
2026-07-15  1:14   ` Klara Modin [this message]
2026-07-15 12:57     ` [External] " Xu Lu
2026-07-17 16:22     ` Anirudh Srinivasan
2025-09-01 11:41 ` [PATCH RESEND 2/2] riscv: mm: Clear cpu in mm_cpumask after local_flush_tlb_all_asid Xu Lu

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