From: Anisa Su <anisa.su887@gmail.com>
To: Dave Jiang <dave.jiang@intel.com>
Cc: Anisa Su <anisa.su887@gmail.com>,
linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org,
nvdimm@lists.linux.dev, Dan Williams <djbw@kernel.org>,
Jonathan Cameron <jic23@kernel.org>,
Davidlohr Bueso <dave@stgolabs.net>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <iweiny@kernel.org>,
Alison Schofield <alison.schofield@intel.com>,
John Groves <John@groves.net>, Gregory Price <gourry@gourry.net>
Subject: Re: [PATCH v11 05/31] cxl/mem: Expose dynamic ram 1 partition in sysfs
Date: Tue, 14 Jul 2026 23:39:15 -0700 [thread overview]
Message-ID: <alcrEwf13LAqRhIm@AnisaLaptop.localdomain> (raw)
In-Reply-To: <8f8bbe74-57a3-4059-93b6-bcc6ba6ddffd@intel.com>
On Fri, Jun 26, 2026 at 04:08:33PM -0700, Dave Jiang wrote:
>
>
> On 6/25/26 4:04 AM, Anisa Su wrote:
> > From: Ira Weiny <iweiny@kernel.org>
> >
> > To properly configure CXL regions user space will need to know the
> > details of the dynamic ram partition.
> >
> > Expose the first dynamic ram partition through sysfs.
> >
> > Signed-off-by: Ira Weiny <iweiny@kernel.org>
> > Signed-off-by: Anisa Su <anisa.su@samsung.com>
> > Reviewed-by: Dave Jiang <dave.jiang@intel.com>
>
> Just a spelling error below
>
oopsie, fixed!
> >
> > ---
> > Changes:
> > 1. Documentation: bump kernel version to 7.3 and date to June 2026
> > 2. Pick up Dave's reviewed-by tag
> > 3. Rename dynamic_ram_a to dynamic_ram_1
> > ---
> > Documentation/ABI/testing/sysfs-bus-cxl | 24 +++++++++++
> > drivers/cxl/core/memdev.c | 57 +++++++++++++++++++++++++
> > 2 files changed, 81 insertions(+)
> >
> > diff --git a/Documentation/ABI/testing/sysfs-bus-cxl b/Documentation/ABI/testing/sysfs-bus-cxl
> > index 16a9b3d2e2c0..435495de409c 100644
> > --- a/Documentation/ABI/testing/sysfs-bus-cxl
> > +++ b/Documentation/ABI/testing/sysfs-bus-cxl
> > @@ -89,6 +89,30 @@ Description:
> > and there are platform specific performance related
> > side-effects that may result. First class-id is displayed.
> >
> > +What: /sys/bus/cxl/devices/memX/dynamic_ram_1/size
> > +Date: June, 2026
> > +KernelVersion: v7.3
> > +Contact: linux-cxl@vger.kernel.org
> > +Description:
> > + (RO) The first Dynamic RAM partition capacity as bytes.
> > +
> > +
> > +What: /sys/bus/cxl/devices/memX/dynamic_ram_1/qos_class
> > +Date: June, 2026
> > +KernelVersion: v7.3
> > +Contact: linux-cxl@vger.kernel.org
> > +Description:
> > + (RO) For CXL host platforms that support "QoS Telemmetry"
>
> Telemetry
>
> DJ
>
> > + this attribute conveys a comma delimited list of platform
> > + specific cookies that identifies a QoS performance class
> > + for the partition of the CXL mem device. These
> > + class-ids can be compared against a similar "qos_class"
> > + published for a root decoder. While it is not required
> > + that the endpoints map their local memory-class to a
> > + matching platform class, mismatches are not recommended
> > + and there are platform specific performance related
> > + side-effects that may result. First class-id is displayed.
> > +
> >
> > What: /sys/bus/cxl/devices/memX/serial
> > Date: January, 2022
> > diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c
> > index 71602820f896..20417db933aa 100644
> > --- a/drivers/cxl/core/memdev.c
> > +++ b/drivers/cxl/core/memdev.c
> > @@ -101,6 +101,19 @@ static ssize_t pmem_size_show(struct device *dev, struct device_attribute *attr,
> > static struct device_attribute dev_attr_pmem_size =
> > __ATTR(size, 0444, pmem_size_show, NULL);
> >
> > +static ssize_t dynamic_ram_1_size_show(struct device *dev, struct device_attribute *attr,
> > + char *buf)
> > +{
> > + struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
> > + struct cxl_dev_state *cxlds = cxlmd->cxlds;
> > + unsigned long long len = cxl_part_size(cxlds, CXL_PARTMODE_DYNAMIC_RAM_1);
> > +
> > + return sysfs_emit(buf, "%#llx\n", len);
> > +}
> > +
> > +static struct device_attribute dev_attr_dynamic_ram_1_size =
> > + __ATTR(size, 0444, dynamic_ram_1_size_show, NULL);
> > +
> > static ssize_t serial_show(struct device *dev, struct device_attribute *attr,
> > char *buf)
> > {
> > @@ -443,6 +456,25 @@ static struct attribute *cxl_memdev_pmem_attributes[] = {
> > NULL,
> > };
> >
> > +static ssize_t dynamic_ram_1_qos_class_show(struct device *dev,
> > + struct device_attribute *attr, char *buf)
> > +{
> > + struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
> > + struct cxl_dev_state *cxlds = cxlmd->cxlds;
> > +
> > + return sysfs_emit(buf, "%d\n",
> > + part_perf(cxlds, CXL_PARTMODE_DYNAMIC_RAM_1)->qos_class);
> > +}
> > +
> > +static struct device_attribute dev_attr_dynamic_ram_1_qos_class =
> > + __ATTR(qos_class, 0444, dynamic_ram_1_qos_class_show, NULL);
> > +
> > +static struct attribute *cxl_memdev_dynamic_ram_1_attributes[] = {
> > + &dev_attr_dynamic_ram_1_size.attr,
> > + &dev_attr_dynamic_ram_1_qos_class.attr,
> > + NULL,
> > +};
> > +
> > static ssize_t ram_qos_class_show(struct device *dev,
> > struct device_attribute *attr, char *buf)
> > {
> > @@ -519,6 +551,29 @@ static struct attribute_group cxl_memdev_pmem_attribute_group = {
> > .is_visible = cxl_pmem_visible,
> > };
> >
> > +static umode_t cxl_dynamic_ram_1_visible(struct kobject *kobj, struct attribute *a, int n)
> > +{
> > + struct device *dev = kobj_to_dev(kobj);
> > + struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
> > + struct cxl_dpa_perf *perf = part_perf(cxlmd->cxlds, CXL_PARTMODE_DYNAMIC_RAM_1);
> > +
> > + if (a == &dev_attr_dynamic_ram_1_qos_class.attr &&
> > + (!perf || perf->qos_class == CXL_QOS_CLASS_INVALID))
> > + return 0;
> > +
> > + if (a == &dev_attr_dynamic_ram_1_size.attr &&
> > + (!cxl_part_size(cxlmd->cxlds, CXL_PARTMODE_DYNAMIC_RAM_1)))
> > + return 0;
> > +
> > + return a->mode;
> > +}
> > +
> > +static struct attribute_group cxl_memdev_dynamic_ram_1_attribute_group = {
> > + .name = "dynamic_ram_1",
> > + .attrs = cxl_memdev_dynamic_ram_1_attributes,
> > + .is_visible = cxl_dynamic_ram_1_visible,
> > +};
> > +
> > static umode_t cxl_memdev_security_visible(struct kobject *kobj,
> > struct attribute *a, int n)
> > {
> > @@ -547,6 +602,7 @@ static const struct attribute_group *cxl_memdev_attribute_groups[] = {
> > &cxl_memdev_attribute_group,
> > &cxl_memdev_ram_attribute_group,
> > &cxl_memdev_pmem_attribute_group,
> > + &cxl_memdev_dynamic_ram_1_attribute_group,
> > &cxl_memdev_security_attribute_group,
> > NULL,
> > };
> > @@ -555,6 +611,7 @@ void cxl_memdev_update_perf(struct cxl_memdev *cxlmd)
> > {
> > sysfs_update_group(&cxlmd->dev.kobj, &cxl_memdev_ram_attribute_group);
> > sysfs_update_group(&cxlmd->dev.kobj, &cxl_memdev_pmem_attribute_group);
> > + sysfs_update_group(&cxlmd->dev.kobj, &cxl_memdev_dynamic_ram_1_attribute_group);
> > }
> > EXPORT_SYMBOL_NS_GPL(cxl_memdev_update_perf, "CXL");
> >
>
next prev parent reply other threads:[~2026-07-15 6:39 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-25 11:04 DCD: Add support for Dynamic Capacity Devices (DCD) Anisa Su
2026-06-25 11:04 ` [PATCH v11 01/31] cxl/mbox: Flag " Anisa Su
2026-06-26 21:43 ` Dave Jiang
2026-06-25 11:04 ` [PATCH v11 02/31] cxl/mem: Read dynamic capacity configuration from the device Anisa Su
2026-06-26 22:26 ` Dave Jiang
2026-06-25 11:04 ` [PATCH v11 04/31] cxl/core: Enforce partition order/simplify partition calls Anisa Su
2026-06-26 22:37 ` Dave Jiang
2026-06-25 11:04 ` [PATCH v11 05/31] cxl/mem: Expose dynamic ram 1 partition in sysfs Anisa Su
2026-06-26 23:08 ` Dave Jiang
2026-07-15 6:39 ` Anisa Su [this message]
2026-06-25 11:04 ` [PATCH v11 06/31] cxl/port: Add 'dynamic_ram_1' to endpoint decoder mode Anisa Su
2026-06-25 11:04 ` [PATCH v11 07/31] cxl/region: Add DC DAX region support Anisa Su
2026-06-26 23:18 ` Dave Jiang
2026-06-25 11:04 ` [PATCH v11 08/31] cxl/events: Split event msgnum configuration from irq setup Anisa Su
2026-06-25 11:04 ` [PATCH v11 09/31] cxl/pci: Factor out interrupt policy check Anisa Su
2026-06-25 11:04 ` [PATCH v11 10/31] cxl/mem: Configure dynamic capacity interrupts Anisa Su
2026-07-07 21:51 ` Cheatham, Benjamin
2026-07-15 21:31 ` Anisa Su
2026-06-25 11:04 ` [PATCH v11 11/31] cxl/core: Return endpoint decoder information from region search Anisa Su
2026-06-25 11:04 ` [PATCH v11 12/31] cxl/mem: Set up framework for handling DC Events Anisa Su
2026-06-26 21:54 ` Dave Jiang
2026-07-16 4:08 ` Anisa Su
2026-06-25 11:04 ` [PATCH v11 13/31] cxl/mem: Add 20 second timeout for stalled DC_ADD_CAPACITY chains Anisa Su
2026-06-30 21:11 ` Dave Jiang
2026-07-16 4:55 ` Anisa Su
2026-06-25 11:04 ` [PATCH v11 14/31] cxl/extent: Handle DC Add Capacity events Anisa Su
2026-07-29 7:54 ` Anisa Su
2026-06-25 11:04 ` [PATCH v11 15/31] cxl/mem: Drop misaligned DCD extent groups Anisa Su
2026-06-30 21:23 ` Dave Jiang
2026-06-25 11:04 ` [PATCH v11 16/31] cxl/extent: Validate DC extent partition Anisa Su
2026-06-30 22:49 ` Dave Jiang
2026-06-25 11:04 ` [PATCH v11 17/31] cxl/mem: Enforce tag-group semantics Anisa Su
2026-06-25 11:04 ` [PATCH v11 18/31] cxl/extent: Handle DC Release Capacity events Anisa Su
2026-06-25 11:04 ` [PATCH v11 19/31] cxl/extent: Enforce cross-region tag uniqueness Anisa Su
2026-06-25 11:04 ` [PATCH v11 20/31] cxl/region/extent: Expose dc_extent information in sysfs Anisa Su
2026-06-25 11:04 ` [PATCH v11 21/31] cxl + dax: Surface dax_resources on DCD Add Capacity events Anisa Su
2026-06-25 11:04 ` [PATCH v11 22/31] cxl + dax: Release dax_resources on DCD Release " Anisa Su
2026-06-25 11:05 ` [PATCH v11 23/31] dax/bus: Factor out dev dax resize logic Anisa Su
2026-06-25 11:05 ` [PATCH v11 24/31] dax/bus: Add uuid sysfs attribute to dax devices Anisa Su
2026-06-30 23:21 ` Dave Jiang
2026-06-25 11:05 ` [PATCH v11 25/31] dax/bus: Reject resize on DC dax devices and enforce 0-size creation Anisa Su
2026-06-25 11:05 ` [PATCH v11 26/31] dax/bus: Tag-aware uuid claim and show on DC dax devices Anisa Su
2026-06-25 11:05 ` [PATCH v11 27/31] cxl/region: Read existing extents on region creation Anisa Su
2026-06-25 11:05 ` [PATCH v11 28/31] cxl/mem: Trace Dynamic capacity Event Record Anisa Su
2026-06-25 11:05 ` [PATCH v11 29/31] tools/testing/cxl: Make event logs dynamic Anisa Su
2026-06-25 11:05 ` [PATCH v11 30/31] tools/testing/cxl: Add DC Regions to mock mem data Anisa Su
2026-06-25 11:05 ` [PATCH v11 31/31] Documentation/cxl: Document DCD extent handling and DC-backed DAX regions Anisa Su
2026-06-25 18:00 ` [PATCH v11 03/31] cxl/cdat: Gather DSMAS data for DCD partitions Anisa Su
2026-06-26 22:30 ` Dave Jiang
2026-07-15 6:37 ` Anisa Su
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