From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-lj1-f171.google.com (mail-lj1-f171.google.com [209.85.208.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1BE3E41BA90 for ; Wed, 15 Jul 2026 18:22:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.171 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784139752; cv=none; b=tOGpPAs57E1sqQStcZqZ9ndApyaQhFF463Nm3bsugc1IWVAr8DWuxPpZ+1izmILiSYPkUJN7x9BwwQhZ47FJdCh3Ce/c/cvpUvZtz3sataqxep44SoMGf0Lxe1daDzGWKcn51s3ybad4xEkG+hdoznvnX5ENS2SxcBPqYAEO5Jc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784139752; c=relaxed/simple; bh=Bnj6jIOQhuRhOUhIK3DfaucI1dbDKSd2Grt1d/Vl2Y0=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=AP+im+Q/ks+tmZvQ78nx8zhfIHabUOJ8lhgTcEbbv/BVPujQdT9hUOuf5BrwLwmUBKatmsZSQ+XOR10KB57nx0sCJdRCAFU2fP+vEi3Ul0bOFxWi6nvQYmzMbhJtRX7CXncH03cat3BbSU5run0uV6moD8x/mqom2NiusdR3g7Y= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=O4sp/ild; arc=none smtp.client-ip=209.85.208.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="O4sp/ild" Received: by mail-lj1-f171.google.com with SMTP id 38308e7fff4ca-39c8dbf4ef0so49892021fa.2 for ; Wed, 15 Jul 2026 11:22:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1784139746; x=1784744546; darn=vger.kernel.org; h=in-reply-to:content-disposition:content-type:mime-version :references:message-id:subject:cc:to:from:date:from:to:cc:subject :date:message-id:reply-to:content-type; bh=TOZk9QruTQyTuzhFKvlY61eCbbJ/6Q27kBXayZAfD38=; b=O4sp/ildC2/Tnxxa/QYJ0BEWZc4Zxf5VaL1ai09IOp2Su98jpJ8RdgXwFDFS/QJYgt SUN0NBgElEU/trOazALvW1A0xo8312bc+ZVnyfhMK4bV0Csa8TPCpDbxq8mvWDG/bgpM vdfdqpidUbDHub2zMfGNyrLemEsWSgSvG33ZOLyUW/Hvd0ruD0YuSa/26dbEIFetW94T oaUw644BuL1L+tK9O9+y0Ggjr3IFO3Y+8aAVFu8EmvTAt02hAJRz7RdU88+jW8o8bSB5 uyWz61TTD4KwCNibfzPoSjNubg7zdqEftXDzobpbkgahPo2alVeM1Zy+vZKIf1Ku78TW sXWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784139746; x=1784744546; h=in-reply-to:content-disposition:content-type:mime-version :references:message-id:subject:cc:to:from:date:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=TOZk9QruTQyTuzhFKvlY61eCbbJ/6Q27kBXayZAfD38=; b=B7MbOVLL8JIF8e0TQWqKW5Ad7cSYsWvRTyW3v5tNRUAE3AF0lA+Drhh7qEbp0bVS6G 3WwwSdfhcVAfLxP5UXTyyuEAx/L0glqvgXgAyVqWU70M9+uyv38iVOHSF4GBRO/mhO4y reFUDXF0eNUw4MlLwWbpOf1JmI5cHZumoWgO+vj0IZl9MRXxYn5JrpbNBE1g/3/LHDsV J3j6AiPmwWpXiC1XmWC6r71FR4InL5s6g8j8kCn7LvwSZgVxfyrCzQxWoybNitqV5N9+ 3qSgnwkoQfCaQnSceqZTwwbBhC3eKqviXKJhlqLKaMW16EATEQ2im1QpjT+LlEKAGf2Q Yb1w== X-Forwarded-Encrypted: i=1; AHgh+Rq640zAVMmCxBpPlcLjd3Cfj45gxIYuIWFHWupKPbCxfXtBqgh3iBPMZfmRFighrOWjFCs7anhy9yt72bo=@vger.kernel.org X-Gm-Message-State: AOJu0Yx+OQDLrJEPzzwNMcMgEC4ihITp+vsOuIDCQFdM0l+ODTOyHMJx cBSq0z98O65ORimURye0b13Q3skgrJ1XKGqIuYBhBctqDXbz83u6PUMC X-Gm-Gg: AfdE7cmZCrxH5C7xyMj3PYPm/b6rsTdHt9O6bfoxUfZIiZ77f/X49TSREGABHIacYsa f460K1MP9hrVPCKu/y88WRNPy7DOin6WqjzfxhXm5zladKQpql3pYSZGNyNzdUc7HiBz/yV6S00 RfTy3SC4UTI9Ps3qlXqeHRmwX1uyfCMlix6OnZ9sSvJctz71em3QDGGXJVJ4y6mKs1Cwd0SbGLE +YrF39JzkZZSUAU9Myoj8AsNngb8I8EkBNMXwVSRFiojr/5G3FyNW5h44RYKzc6/MDvICNkfvT/ YtFGVidD9Od08WEQD7XGn7wfE+silKuQHXk+VLT4+TElmwNg6oNgnyizPbR+nFLvXwNQp+ndvNY 30X1L1NjeHIoIviFG0piQ9ararkojKFNcdsVSoqLqq1EGmjrJq+rzGu0+hP7DOzLSla4zfsBdDJ lDwgC+zAmug8ryfZMMF600mEEf1Ag= X-Received: by 2002:a2e:a98e:0:b0:39c:628c:15ec with SMTP id 38308e7fff4ca-39daa822609mr19800191fa.23.1784139745916; Wed, 15 Jul 2026 11:22:25 -0700 (PDT) Received: from localhost (soda.int.kasm.eu. [2001:678:a5c:1202:7b92:9ac1:b9ef:5287]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-39c849174ebsm39803721fa.7.2026.07.15.11.22.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jul 2026 11:22:23 -0700 (PDT) Date: Wed, 15 Jul 2026 20:22:22 +0200 From: Klara Modin To: Xu Lu Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, apw@canonical.com, joe@perches.com Subject: Re: [PATCH v2 2/3] riscv: mm: Apply Svinval in update_mmu_cache() Message-ID: References: <20260715132009.10634-1-luxu.kernel@bytedance.com> <20260715132009.10634-3-luxu.kernel@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260715132009.10634-3-luxu.kernel@bytedance.com> On 2026-07-15 21:20:08 +0800, Xu Lu wrote: > Use Svinval in update_mmu_cache_range() when the extension is available. > > Signed-off-by: Xu Lu This version works fine for me. Thanks, Tested-by: Klara Modin > --- > arch/riscv/include/asm/pgtable.h | 8 ++++++++ > arch/riscv/include/asm/tlbflush.h | 18 ++++++++++++++++++ > arch/riscv/mm/tlbflush.c | 18 ------------------ > 3 files changed, 26 insertions(+), 18 deletions(-) > > diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h > index 9926556099ae..823805cc465a 100644 > --- a/arch/riscv/include/asm/pgtable.h > +++ b/arch/riscv/include/asm/pgtable.h > @@ -578,6 +578,14 @@ static inline void update_mmu_cache_range(struct vm_fault *vmf, > if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SVVPTC)) > return; > > + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SVINVAL)) { > + local_sfence_w_inval(); > + while (nr--) > + local_sinval_vma(address + nr * PAGE_SIZE, asid); > + local_sfence_inval_ir(); > + return; > + } > + > /* > * The kernel assumes that TLBs don't cache invalid entries, but > * in RISC-V, SFENCE.VMA specifies an ordering constraint, not a > diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h > index 7c2cd5cc92d3..9636d07fe9ee 100644 > --- a/arch/riscv/include/asm/tlbflush.h > +++ b/arch/riscv/include/asm/tlbflush.h > @@ -20,6 +20,24 @@ static inline unsigned long get_mm_asid(struct mm_struct *mm) > return mm ? cntx2asid(atomic_long_read(&mm->context.id)) : FLUSH_TLB_NO_ASID; > } > > +static inline void local_sfence_inval_ir(void) > +{ > + asm volatile(SFENCE_INVAL_IR() ::: "memory"); > +} > + > +static inline void local_sfence_w_inval(void) > +{ > + asm volatile(SFENCE_W_INVAL() ::: "memory"); > +} > + > +static inline void local_sinval_vma(unsigned long vma, unsigned long asid) > +{ > + if (asid != FLUSH_TLB_NO_ASID) > + asm volatile(SINVAL_VMA(%0, %1) : : "r" (vma), "r" (asid) : "memory"); > + else > + asm volatile(SINVAL_VMA(%0, zero) : : "r" (vma) : "memory"); > +} > + > static inline void local_flush_tlb_all(void) > { > __asm__ __volatile__ ("sfence.vma" : : : "memory"); > diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c > index 73c226f719c7..962db300a166 100644 > --- a/arch/riscv/mm/tlbflush.c > +++ b/arch/riscv/mm/tlbflush.c > @@ -11,24 +11,6 @@ > > #define has_svinval() riscv_has_extension_unlikely(RISCV_ISA_EXT_SVINVAL) > > -static inline void local_sfence_inval_ir(void) > -{ > - asm volatile(SFENCE_INVAL_IR() ::: "memory"); > -} > - > -static inline void local_sfence_w_inval(void) > -{ > - asm volatile(SFENCE_W_INVAL() ::: "memory"); > -} > - > -static inline void local_sinval_vma(unsigned long vma, unsigned long asid) > -{ > - if (asid != FLUSH_TLB_NO_ASID) > - asm volatile(SINVAL_VMA(%0, %1) : : "r" (vma), "r" (asid) : "memory"); > - else > - asm volatile(SINVAL_VMA(%0, zero) : : "r" (vma) : "memory"); > -} > - > /* > * Flush entire TLB if number of entries to be flushed is greater > * than the threshold below. > -- > 2.39.5 >