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The driver stored CPU-endian u32 values > into them directly, which is both wrong (the engine would see > byte-swapped lengths/addresses) and flagged by sparse as a base-type > mismatch. > > Wrap those stores in cpu_to_be32() so the values are little->big > converted. The final-frame bit is now passed as the "final" argument of > fill_cfd_frame() (as fsl_re_prep_dma_memcpy already did) and set in CPU > order before the single cpu_to_be32() store, replacing the previous > read-modify-write of the __be32 efrl32 field. Can you split two patches, one add cpu_le_be32(), other change to call fill_cfd_frame() Frank > > Reported-by: kernel test robot > Fixes: https://lore.kernel.org/oe-kbuild-all/202008111749.yy85rFMD%25lkp@intel.com/ > Assisted-by: opencode:hy3-free > Signed-off-by: Rosen Penev > --- > drivers/dma/fsl_raid.c | 29 +++++++++++++++-------------- > 1 file changed, 15 insertions(+), 14 deletions(-) > > diff --git a/drivers/dma/fsl_raid.c b/drivers/dma/fsl_raid.c > index 99945845d8b5..888f55b672a5 100644 > --- a/drivers/dma/fsl_raid.c > +++ b/drivers/dma/fsl_raid.c > @@ -242,9 +242,9 @@ static void fill_cfd_frame(struct fsl_re_cmpnd_frame *cf, u8 index, > u32 efrl = length & FSL_RE_CF_LENGTH_MASK; > > efrl |= final << FSL_RE_CF_FINAL_SHIFT; > - cf[index].efrl32 = efrl; > - cf[index].addr_high = upper_32_bits(addr); > - cf[index].addr_low = lower_32_bits(addr); > + cf[index].efrl32 = cpu_to_be32(efrl); > + cf[index].addr_high = cpu_to_be32(upper_32_bits(addr)); > + cf[index].addr_low = cpu_to_be32(lower_32_bits(addr)); > } > > static struct fsl_re_desc *fsl_re_init_desc(struct fsl_re_chan *re_chan, > @@ -256,9 +256,10 @@ static struct fsl_re_desc *fsl_re_init_desc(struct fsl_re_chan *re_chan, > dma_async_tx_descriptor_init(&desc->async_tx, &re_chan->chan); > INIT_LIST_HEAD(&desc->node); > > - desc->hwdesc.fmt32 = FSL_RE_FRAME_FORMAT << FSL_RE_HWDESC_FMT_SHIFT; > - desc->hwdesc.lbea32 = upper_32_bits(paddr); > - desc->hwdesc.addr_low = lower_32_bits(paddr); > + desc->hwdesc.fmt32 = cpu_to_be32(FSL_RE_FRAME_FORMAT << > + FSL_RE_HWDESC_FMT_SHIFT); > + desc->hwdesc.lbea32 = cpu_to_be32(upper_32_bits(paddr)); > + desc->hwdesc.addr_low = cpu_to_be32(lower_32_bits(paddr)); > desc->cf_addr = cf; > desc->cf_paddr = paddr; > > @@ -374,11 +375,11 @@ static struct dma_async_tx_descriptor *fsl_re_prep_dma_genq( > for (i = 2, j = 0; j < save_src_cnt; i++, j++) > fill_cfd_frame(cf, i, len, src[j], 0); > > + /* Fill the last frame and mark it final */ > if (cont_q) > - fill_cfd_frame(cf, i++, len, dest, 0); > - > - /* Setting the final bit in the last source buffer frame in CFD */ > - cf[i - 1].efrl32 |= 1 << FSL_RE_CF_FINAL_SHIFT; > + fill_cfd_frame(cf, i, len, dest, 1); > + else > + fill_cfd_frame(cf, i - 1, len, src[j - 1], 1); > > return &desc->async_tx; > } > @@ -504,16 +505,16 @@ static struct dma_async_tx_descriptor *fsl_re_prep_dma_pq( > p[save_src_cnt + 2] = 1; > fill_cfd_frame(cf, i++, len, dest[0], 0); > fill_cfd_frame(cf, i++, len, dest[1], 0); > - fill_cfd_frame(cf, i++, len, dest[1], 0); > + fill_cfd_frame(cf, i++, len, dest[1], 1); > } else { > dev_err(re_chan->dev, "PQ tx continuation error!\n"); > return NULL; > } > + } else { > + /* Mark the last source buffer frame final */ > + fill_cfd_frame(cf, i - 1, len, src[j - 1], 1); > } > > - /* Setting the final bit in the last source buffer frame in CFD */ > - cf[i - 1].efrl32 |= 1 << FSL_RE_CF_FINAL_SHIFT; > - > return &desc->async_tx; > } > > -- > 2.55.0 >