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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3142a1de21asm1298743eec.23.2026.07.16.20.02.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Jul 2026 20:02:25 -0700 (PDT) Date: Thu, 16 Jul 2026 20:02:23 -0700 From: Qiang Yu To: Konrad Dybcio Cc: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH RFC v4 9/9] arm64: dts: qcom: glymur: Wire PCIe3a/3b to shared Gen5x8 PHY Message-ID: References: <20260518-link_mode_0519-v4-0-269cd73cc5d1@oss.qualcomm.com> <20260518-link_mode_0519-v4-9-269cd73cc5d1@oss.qualcomm.com> <6802dc29-d783-40df-bbb8-8b2dbd94be29@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzE3MDAyNiBTYWx0ZWRfX8iG4IBrn/lF+ Odkmcu9iqUzE14Zq6A6+T2UZFYyQSckP7pGI5WQQHjbIPRM+OipWfTXka62QT4+wQ8AyrUV81Si Zq1lbYrFTlnQnYLE1FDuyYgJV9iwikFMYKDHgoIYLHcb4zkzHfDsuhs6CZhhHDL4NHvIRwV8X3c 4e2YLaSXHKlJh7LrQpvTshzXGYHcKT2XMGp3FA2ZxYvNUegNAtnJY3pjTG5n7QrDGLm3+IGeu0d avwCs/Fx4lqe8nT8tU7VRGHYE0H/p0jNTR1lj+hdYaeJmoxljWY47a2sNRdbbcCyVD5emOyLNFr cympcksGA4+oe2NpON561hJEtHvNSxQWEI/qPVdhYOX9qmrrjaXv9nQUwuDsFWDJOVJEUbql3EG 6TTvjjHiNajZutOgb1JqvRStS8VqPMSP2RtE0bH6TI+SI5X4HxU5DIPcYSkAIgzJ5OuaponUQ7M hvPJkWxbwz5Il3a5uuQ== X-Authority-Analysis: v=2.4 cv=JJ8LdcKb c=1 sm=1 tr=0 ts=6a599b43 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=kj9zAlcOel0A:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=p66J1l9MvY5bjjRUTH8A:9 a=CjuIK1q_8ugA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzE3MDAyNiBTYWx0ZWRfX9qwfE1nIhvGv AQyJ71/gYvRRh89WdtFGcWJi1PXqh2b7MXLOUtUZKDGX/Atc1+1PEBRlHfF4kvOiELEj8vhm6vH p0cWXt/IIAilIO8nGbays1OIgzX0u6Y= X-Proofpoint-ORIG-GUID: UQm4kqQMzc4Bc4TBu7TrUqDIHnKi4FHR X-Proofpoint-GUID: UQm4kqQMzc4Bc4TBu7TrUqDIHnKi4FHR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-16_08,2026-07-15_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 adultscore=0 suspectscore=0 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607170026 On Fri, Jul 10, 2026 at 03:25:37PM +0200, Konrad Dybcio wrote: > On 7/10/26 3:11 PM, Qiang Yu wrote: > > On Fri, Jul 10, 2026 at 10:44:20AM +0200, Konrad Dybcio wrote: > >> On 7/10/26 4:19 AM, Qiang Yu wrote: > >>> On Mon, Jun 29, 2026 at 11:20:07AM +0200, Konrad Dybcio wrote: > >>>> On 6/29/26 7:05 AM, Qiang Yu wrote: > >>>>> On Wed, Jun 17, 2026 at 01:19:49PM +0200, Konrad Dybcio wrote: > >>>>>> On 5/19/26 7:47 AM, Qiang Yu wrote: > >>>>>>> Glymur PCIe3 uses a single shared Gen5x8 QMP PHY block. Model PCIe3a and > >>>>>>> PCIe3b as consumers of that shared PHY provider instead of separate PHY > >>>>>>> nodes. > > [...] > > >>>>>>> + linux,pci-domain = <3>; > >>>>>>> + num-lanes = <8>; > >>>>>> > >>>>>> Is it fine to keep num-lanes 8 here even for configurations with > >>>>>> bifurcated PHY? > >>>>>> > >>>>>> I would assume so, given essentially this is a x8 host, whose 4 > >>>>>> lanes may simply be effectively NC > >>>>>> > >>>>> Actually, on existing platforms, the PCIe3a and PCIe3b controllers are > >>>>> never enabled at the same time. When PCIe3a is exposed, it is always in an > >>>>> x8 slot. But if we have a x4+x4 platform in future, we can simply override > >>>>> num-lanes to 4 in the board.dts. > >>>> > >>>> My question is whether that will be necessary - if yes, sure, we > >>>> can do it, but if not, we can conclude on this early and not have > >>>> to fight over it in a couple months > >>>> > >>> I think we do need to override it in that case. If both PCIe3a and PCIe3b > >>> are enabled in x4+x4 mode but PCIe3a keeps num-lanes = <8>, userspace > >>> will see an 8-lane slot. If an x8-capable EP is connected to that slot, > >>> both ends will advertise x8 support, but the link is up at x4. That looks > >>> like a genuine bug from the user's point of view. > >> > >> Do we know what's advertised on x86 PCs with bifurcated lanes? > >> > > On QCB, it advertise x8. On CRD, PCIe3a is hidden. > > No no, I meant to ask whether we know what the userspace gets to see on > e.g. an AMD system with a bifurcated slot. I would expect that LnkCap > may report a different value, but not necessarily. I would assume we > should probably mimic whatever that does, unless the spec takes a > stance on what should be done. > I don't have any AMD/Intel hardware with a bifurcated slot at hand, and I couldn't find an lspci example showing what LnkCap reports in that case either, so I can't confirm what x86 does here. But can you elaborate on what is the benefits to set it to 8 in x4+x4 mode? - Qiang Yu